Pipelined ADC Design and Enhancement Techniques

Abstract

Library of Congress Control Number: 2010920320# Springer ScienceþBusiness Media B.V. 2010 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.Cover design: WMXDesign GmbH, Heidelberg, GermanyPrinted on acid-free paper Springer is part of Springer ScienceþBusiness Media (www.springer.com) PrefacePipelined ADCs have seen a tremendous growth in innovation and scope over the past few years. As such understanding both the basic concepts and the leading edge techniques required to realize pipelined ADCs which meet the challenging specifications of today's market and applications is required. While pipelined ADCs are popular circuit blocks, beyond publications in periodicals there are only a few condensed resources which are dedicated to education in the area. This book aims to help bridge the gap with a thorough discussion of pipelined ADCs.This book is targeted to both the beginner and expert looking to acquire knowledge in pipelined ADCs. In the first section of this book, a tutorial discussion of several key design tradeoffs involved in designing a pipelined ADC is given. The discussion is presented with sufficient detail so as to allow those with only introductory knowledge of pipelined ADCs to quickly understand the limiting factors which motivate research into methods which enhance the performance of pipelined ADCs. In the second half of this book a detailed overview and discussion of four state-of-the-art pipelined ADCs with silicon implementations and measured results is given. The innovations include: a technique to rapidly digitally correct gain + DAC errors in a pipelined ADC, an architecture to enable a single ADC to be designed to achieve low power for a very wide range of sampling rates, a circuit technique to eliminate front-end sample-and-holds in pipelined ADCs, and finally a very low power pipelined ADC architecture based on capacitive charge pumps.The innovations presented in this book provides several tools which can be of great use to help a pipelined ADC designer deliver a design with good linearity, broad application, and very low power.v

1 5 Bit Stage 12 Bit Pipeline ADC Design with Foreground Calibration

“…Calibration of these unwanted conditions can be obtained by opamp gain and matching capacitor treatment. As new deep sub-micron technologies support digital circuits with low power consumption and area relatedly previous technologies, digital calibration has become an important issue for low powered and much linear ADCs [6]. In the choice of calibration technique, several papers in the literature were searched to decide for this paper.…”

“…The downside of foreground calibration is to have ADC been offline for each calibration attempt. This makes the calibration impossible for some special applications [6].…”

“…This paper considers the foreground calibration as presented in the following Fig. 2 [6]. Foreground calibration (LMS: Least Mean Square) [6].…”

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

“…High-frequency and high-resolution pipelined ADCs have imposed stringent requirements on clock designs, including low jitter property for SHA, precise duty cycle for pipeline stages, and non-overlapping clocks for voltage sampling and charge transferring [4], [20], [21]. First, clock jitter leads to sample-to-sample variations, which can result in prominent errors for IF-sampling applications because of the high slew rate of fast changing input signals.…”

Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

“…The pipeline architecture covers numerous signals that process applications used in communication, instrumentation, and imaging systems because the architecture is classified as high-speed and high-accuracy [1]. This architecture is designed for power-efficient high-speed conversion of wide bandwidth input signals in the range of 10 to 100 mega samples per second with medium to high resolution bits of around 8-to 14-bits resolution [2]. As discussed in [3], a pipeline ADC is an open-loop architecture with a small inherent latency of between 4 and 6 clock cycles and has a direct relationship with the input signal and the output code.…”