Abstract-A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles.
Abstract-A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves 10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.
In this paper, we propose a Singular-Value-Decomposition-based variable-resolution Analog to Digital Converter (ADC) bit allocation design for a single-user Millimeter wave massive Multiple-Input Multiple-Output receiver. We derive the optimality condition for bit allocation under a power constraint. This condition ensures optimal receiver performance in the Mean Squared Error (MSE) sense. We derive the MSE expression and show that it approaches the Cramer-Rao Lower Bound (CRLB). The CRLB is seen to be a function of the analog combiner, the digital combiner, and the bit allocation matrix. We attempt to minimize the CRLB with respect to the bit allocation matrix by making suitable assumptions regarding the structure of the combiners. In doing so, the bit allocation design reduces to a set of simple inequalities consisting of ADC bits, channel singular values and covariance of the quantization noise along each RF path. This results in a simple and computationally efficient bit allocation algorithm. Using simulations, we show that the MSE performance of our proposed bit allocation is very close to that of the Full Search (FS) bit allocation. We also show that the computational complexity of our proposed method has an order of magnitude improvement compared to FS and Genetic Algorithm based bit allocation of [1].
Library of Congress Control Number: 2010920320# Springer ScienceþBusiness Media B.V. 2010 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.Cover design: WMXDesign GmbH, Heidelberg, GermanyPrinted on acid-free paper Springer is part of Springer ScienceþBusiness Media (www.springer.com) PrefacePipelined ADCs have seen a tremendous growth in innovation and scope over the past few years. As such understanding both the basic concepts and the leading edge techniques required to realize pipelined ADCs which meet the challenging specifications of today's market and applications is required. While pipelined ADCs are popular circuit blocks, beyond publications in periodicals there are only a few condensed resources which are dedicated to education in the area. This book aims to help bridge the gap with a thorough discussion of pipelined ADCs.This book is targeted to both the beginner and expert looking to acquire knowledge in pipelined ADCs. In the first section of this book, a tutorial discussion of several key design tradeoffs involved in designing a pipelined ADC is given. The discussion is presented with sufficient detail so as to allow those with only introductory knowledge of pipelined ADCs to quickly understand the limiting factors which motivate research into methods which enhance the performance of pipelined ADCs. In the second half of this book a detailed overview and discussion of four state-of-the-art pipelined ADCs with silicon implementations and measured results is given. The innovations include: a technique to rapidly digitally correct gain + DAC errors in a pipelined ADC, an architecture to enable a single ADC to be designed to achieve low power for a very wide range of sampling rates, a circuit technique to eliminate front-end sample-and-holds in pipelined ADCs, and finally a very low power pipelined ADC architecture based on capacitive charge pumps.The innovations presented in this book provides several tools which can be of great use to help a pipelined ADC designer deliver a design with good linearity, broad application, and very low power.v
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