Photonics design tool for advanced CMOS nodes

Abstract

Recently, the authors have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigour that is embodied in the 10 000 to 50 000 design rules that these designs must comply within advanced complementary metal-oxide semiconductor manufacturing. Here, the authors present a photonic design automation tool which allows automatic generation of layouts without design-rule violations. This tool is written in SKILL, the native language of the mainstream electric design automation software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. For the first time the authors present an algorithm for removal of design-rule violations from photonic layouts based on Manhattan discretisation, Boolean and sizing operations. This algorithm is not limited to the implementation in SKILL, and can in principle be implemented in any scripting language. Connectivity is achieved with software-defined waveguide ports and low-level procedures that enable auto-routing of waveguide connections.Comment: 5 pages, 10 figure

Silicon Photonics Circuit Design: Methods, Tools and Challenges

“…PCells are usually defined in a scripting language. This can be a proprietary language such as SKILL in Cadence, Ample in Mentor Graphics Pyxis, SPT in Phoenix Software, or an established standard language such as Python, which is used in in IPKISS, KLayout, and Synopsys PyCell Studio, Tcl, used by Synopsys and Mentor Graphics or Matlab . Even with standard languages, code will be specific to the application programming interface (API) of the particular tool ( e.g ., Python code to add a polygon will differ between tools as there is no standardization).…”

“…When the mask layout is sent to the fab for fabrication, the geometric patterns are usually adjusted so they can be written onto a photomask, or in the case of e‐beam lithography, directly onto the silicon chip. In this step, the geometric primitives are fractured into smaller polygons, and depending on the writing strategy all geometries also need to be rasterized/staircased to a fine grid . This process can have some influence on the quality of the patterns, especially in photonic layouts with many curvilinear shapes.…”

“…There is also growing trend to implement photonic design directly into an established EDA tool, giving the photonics designers all the tools of an electronics designer. However, as we discuss in detail in section the differences between photonics and electronics make it difficult to capture some aspects of a photonics design accurately in a pure EDA tool, and workarounds/customizations are needed to approximate photonics in an electronics design environment.…”

High-speed polysilicon CMOS photodetector for telecom and datacom

“…A resonant microring detector with a diameter of 24 lm is designed to increase the interaction length for a more compact device. The device was implemented using our photonic design software 23 and was fabricated in Global Foundry's 45 nm SOI CMOS process. Details on the resonator design and substrate release process used for these SOI devices with thin buried oxide layer can be found in Ref.…”

Resonance-enhanced waveguide-coupled silicon-germanium detector

“…6,7 An alternative approach consists of designing photonic components in existing CMOS nodes without violating any design rule and without requiring any modifications to the process flow-the so-called zero-change CMOS. 8,9 Within the GlobalFoundries (formerly IBM) 45 nm 12SOI node, we have recently demonstrated a complete zero-change photonic toolbox comprising waveguides with 5 dB/cm propagation losses, 8 grating-couplers, 10 5 Gbps modulators, 11 and 32 GHz photodetectors. 7 These components enabled the first realization of an optical link between a microprocessor and an external memory.…”