Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies

Fiorelli, Rafaella; Silveira, Fernando; Peralías, E.

doi:10.1145/1601896.1601918

Cited by 2 publications

(2 citation statements)

References 13 publications

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“…A graphical optimization methodology which uses graphical nonlinear programming is proposed, providing essential intuitions in finding the optimum solution. Another optimization methodology, where electromagnetic simulators as Cadence SpectreRF and ASITIC are used as a way to guarantee the accuracy of results, is presented in [16]. Here, the LC-VCO design optimization is based on the gm/ID methodology, where the oscillator design space is studied with the goal of obtaining the optimum design, considering phase noise -consumption trade-off.…”

Section: Fig 2 Lc-vco Topologymentioning

confidence: 99%

Optimization-Based Design of Nano-CMOS LC-VCOs

Pereira

Fino

Coito

et al. 2012

Technological Innovation for Value Creation

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Abstract. This paper introduces a variability-aware methodology for the design of LC-VCOs in Nano-CMOS technologies. The complexity of the design as well as the necessity for having an environment offering the possibility for exploring design trade-offs has led to the development of design methodologies based multi-objective optimization procedures yielding the generation of Pareto-optimal surfaces. The efficiency of the process is granted by using analytical models for both passive and active devices. Although physics-based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization performance index. The usually adopted methodology of considering only optimum solutions for the Pareto surface, may lead to pruning quasi-optimal solutions that may prove to be better, should their sensitivity to process parameter variation be accounted for. In this work we propose starting by generating an extended Pareto surface where both optimum and quasi-optimum solutions are considered. Finally information on the sensitivity to process parameter variations, is used for electing the best design solution.

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Section: Fig 2 Lc-vco Topologymentioning

confidence: 99%

Optimization-Based Design of Nano-CMOS LC-VCOs

Pereira

Fino

Coito

et al. 2012

Technological Innovation for Value Creation

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“…Ramos et al [10] showed a 950 MHz LNA in MI-WI. The authors have presented an RF amplifier for 900 MHz [11] and a 2.4 GHz VCO [12] both designed in MI regions. Lee and Mohammadi [13] presented a 2.4 GHz VCO design in WI whereas Hsieh and Lu [14] designed a 5 GHz receiver front-end in MI and WI.…”

Section: Introductionmentioning

confidence: 99%

LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies

Fiorelli

Peralfas

Silveira³

2011

IEEE Trans. Microwave Theory Techn.

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In this paper, an LC-VCO design optimization methodology based on the g m /I D technique and on the exploration of all inversion regions of the MOS transistor is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semi-empirical models of MOS transistors and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design trade-offs are easily identified. Four LC-VCO designs in different inversion regions in a 90 nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4 GHz VCO operating in moderate inversion. The designed VCO draws 440 µA from a 1.2V power supply and presents a phase noise of −106.2 dBc/Hz at 400 kHz from the carrier.

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Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies

Cited by 2 publications

References 13 publications

Optimization-Based Design of Nano-CMOS LC-VCOs

Optimization-Based Design of Nano-CMOS LC-VCOs

LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies

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