Phase-Change Memory: Performance, Roles and Challenges

Navarro, G.; Bourgeois, G.; Kluge, Julia; Serra, A.; Verdy, Anthonin; Garrione, J.; Cyrille, Marie-Claire; Bernier, Nicolas; Jannaud, Audrey; Sabbione, C.; Bernard, M.; Nolot, Emmanuel; Fillot, F.; Noé, Pierre; Fellouh, L.; Rodriguez, Guillaume; Beugin, V.; Cueto, O.; Castellani, N.; Coignus, J.; Delaye, V.; Socquet-Clerc, C.; Magis, T.; Boixaderas, Christelle; Barnola, S.; Nowak, E.

doi:10.1109/imw.2018.8388845

Cited by 16 publications

(10 citation statements)

References 13 publications

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“…The device characteristics can be tuned through material engineering (doping, etc.). Thus, they have the capability to address the high temperature retention required in embedded applications and the high speed required, for example, in storage class memory applications depending on the elected stack [72,73].…”

Section: Phase Change Memorymentioning

confidence: 99%

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Molas

Nowak

2021

Applied Sciences

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This paper presents an overview of emerging memory technologies. It begins with the presentation of stand-alone and embedded memory technology evolution, since the appearance of Flash memory in the 1980s. Then, the progress of emerging memory technologies (based on filamentary, phase change, magnetic, and ferroelectric mechanisms) is presented with a review of the major demonstrations in the literature. The potential of these technologies for storage applications addressing various markets and products is discussed. Finally, we discuss how the rise of artificial intelligence and bio-inspired circuits offers an opportunity for emerging memory technology and shifts the application from pure data storage to storage and computing tasks, and also enlarges the range of required specifications at the device level due to the exponential number of new systems and architectures.

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Section: Phase Change Memorymentioning

confidence: 99%

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Molas

Nowak

2021

Applied Sciences

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“…These timing parameters are based on a 266MHz memory clock and a DDR2 interface [37] (see also Table 5 for our simulation parameters). Figure 2 illustrates a PCM bank's peripheral structures in detail [17,19,37,41,59,60]. There are 128 peripheral structures, which are shared across all bitlines in the bank.…”

Section: Background On Pcmmentioning

confidence: 99%

“…Figure 2 illustrates a PCM bank's peripheral structures in detail [17,19,37,41,59,60]. There are 128 peripheral structures, which are shared across all bitlines in the bank.…”

Section: Enabling Partition-level Parallelism In Pcmmentioning

confidence: 99%

“…Modern phase change memory (PCM) devices [9,17,30,37,41,59] can serve multiple requests in parallel using different PCM banks [37]. Unfortunately, when two requests go to the same bank, This article appears as part of the ESWEEK-TECS special issue and was presented in the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 2019. they have to be served serially.…”

Section: Introductionmentioning

confidence: 99%

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Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories

Song

Das

Mutlu

et al. 2019

ACM Trans. Embed. Comput. Syst.

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Phase-change memory (PCM) devices have multiple banks to serve memory requests in parallel. Unfortunately, if two requests go to the same bank, they have to be served one after another, leading to lower system performance. We observe that a modern PCM bank is implemented as a collection of partitions that operate mostly independently while sharing a few global peripheral structures, which include the sense amplifiers (to read) and the write drivers (to write). Based on this observation, we propose PALP, a new mechanism that enables partition-level parallelism within each PCM bank, and exploits such parallelism by using the memory controller's access scheduling decisions. PALP consists of three new contributions. First, we introduce new PCM commands to enable parallelism in a bank's partitions in order to resolve the read-write bank conflicts, with no changes needed to PCM logic or its interface. Second, we propose simple circuit modifications that introduce a new operating mode for the write drivers, in addition to their default mode of serving write requests. When configured in this new mode, the write drivers can resolve the read-read bank conflicts, working jointly with the sense amplifiers. Finally, we propose a new access scheduling mechanism in PCM that improves performance by prioritizing those requests that exploit partition-level parallelism over other requests, including the long outstanding ones. While doing so, the memory controller also guarantees starvation-freedom and the PCM's running-average-power-limit (RAPL).We evaluate PALP with workloads from the MiBench and SPEC CPU2017 Benchmark suites. Our results show that PALP reduces average PCM access latency by 23%, and improves average system performance by 28% compared to the state-of-the-art approaches. CCS CONCEPTS• Computer systems organization → Architectures; • Hardware → Memory and dense storage.

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“…Material and stoichiometry engineering in PCM is considered the main factor for boosting the device performances [6]. Materials along the GeTe-Sb2Te3 tie line, such as GeTe [7] or GeSb2Te4 [8], were identified for their high programming speed and they represent possible candidates for SCM applications.…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis in GeTe and GeSbTe based phase-change memory 4 kb arrays targeting storage class memory applications

Lama

Bourgeois

Bernard

et al. 2020

Microelectronics Reliability

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In this work, we propose a reliability analysis targeting the evaluation of the suitability of a Phase-Change Memory (PCM) device for Storage Class Memory (SCM) applications. Thanks to the analysis of programming and endurance characteristics in single devices and 4kb arrays we compare two different GeTe and GeSbTe (αGST) based PCM. The evolution of the phase-change material along cycling is explained by the analysis of subthreshold characteristics and analytical equations based on experimental data for the description of electrical parameters evolution are given. An extrapolation method to evaluate endurance at more than 10 9 cycles required for SCM is described and applied, showing the intrinsic high endurance capability and suitability for SCM applications of αGST wrt GeTe.

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Phase-Change Memory: Performance, Roles and Challenges

Cited by 16 publications

References 13 publications

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories

Reliability analysis in GeTe and GeSbTe based phase-change memory 4 kb arrays targeting storage class memory applications

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