Perturbation analysis for word-length optimization

Constantinides, George A.

doi:10.1109/fpga.2003.1227244

Cited by 50 publications

(58 citation statements)

References 16 publications

(38 reference statements)

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“…On the one hand, the noise produced by each signal is described in terms of the traditional quantization noise model from [12], which is less accurate than [11], and, again, second order statistics are neglected. On the other hand, the expression of the estimated noise power accounts for noise interdependencies, which is a better approach than [7]. The method is tested with an LMS adaptive filter and the accuracy is evaluated graphically.…”

Section: Related Workmentioning

confidence: 99%

“…The work in [7] proposes a hybrid method that combines simulations and analytical techniques to estimate the variance of the noise. The estimator is suitable for non-recursive and recursive algorithms.…”

Section: Related Workmentioning

confidence: 99%

“…However, in the last few years there have been attempts to provide fast estimation methods based on analytical techniques. These approaches can be applied to Linear TimeInvariant (LTI) systems [5,2,6] and to differentiable non-linear systems [7][8][9][10]. As for the noise metric used, they are based on the peak value [10] and on the computation of SQNR [2,7,5,9,8].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fast Fixed-Point Optimization of DSP Algorithms

Caffarena

Carreras

López

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. In this chapter, the fast fixed-point optimization of Digital Signal Processing (DSP) algorithms is addressed. A fast quantization noise estimator is presented. The estimator enables a significant reduction in the computation time required to perform complex fixed-point optimizations, while providing a high accuracy. Also, a methodology to perform fixed-point optimization is developed.Affine Arithmetic (AA) is used to provide a fast Signal-to-Quantization Noise-Ratio (SQNR) estimation that can be used during the fixed-point optimization stage. The fast estimator covers differentiable non-linear algorithms with and without feedbacks. The estimation is based on the parameterization of the statistical properties of the noise at the output of fixed-point algorithms. This parameterization allows relating the fixedpoint formats of the signals to the output noise distribution by means of fast matrix operations. Thus, a fast estimation is achieved and the computation time of the fixed-point optimization process is significantly reduced.The proposed estimator and the fixed-point optimization methodology are tested using a subset of non-linear algorithms, such as vector operations, IIR filter for mean power computation, adaptive filters -for both linear and non-linear system identification -and a channel equalizer. The computation time of fixed-point optimization is boosted by three orders of magnitude while keeping the average estimation error down to 6% in most cases.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fast Fixed-Point Optimization of DSP Algorithms

Caffarena

Carreras

López

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

View full text Add to dashboard Cite

show abstract

“…These methods employed analytical digital noise analysis which is more suitable for Linear Time Invariant (LTI) systems. Constantinides later extended the previous efforts to nonlinear components in a datapath by employing a small signal approach and investigated the effect of precision optimization on power reduction as a by-product of the WL optimization [5]. Again in this work power consumption was not an objective in the optimization heuristic.…”

Section: Introductionmentioning

confidence: 99%

Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Ahmadi

Zwoliński

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great impact on design costs. A combination of both methods is used in this paper in the form of a partitioned shared bus structure, in which every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the FUs as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a MultiObjective Optimization Genetic Algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting an optimal grouping and word-length for each FU in a shared bus system. Results demonstrate that savings can be made in the overall system costs by applying this method.

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“…The benchmarks include: an LMS adaptive filter, as used in [31]; a multi-channel IIR filter and a Costas Loop, as supplied with Xilinx System Generator [23]; a programmable two dimensional 5x5 image convolution on a raster-scanned image, based on that supplied with System Generator; an ADPCM encoder [32]; and a Horner scheme polynomial evaluator. All benchmarks are of a similar hardware complexity when implemented in their time-optimal strategy, area figures relative to the size of a slice are given in Table II. The first results presented evaluate the efficiency of the floorplanning and technology mapping heuristic for the different types of benchmark, in a similar fashion to Section V-A.…”

Section: B Architectural Explorationmentioning

confidence: 99%

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Smith

Constantinides

Cheung

2008

IEEE Trans. VLSI Syst.

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Abstract-This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. The approach detailed provides a formal mechanism to explore future technology nodes.

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Perturbation analysis for word-length optimization

Abstract: This paper introduces a design tool and its associated

Cited by 50 publications

References 16 publications

Fast Fixed-Point Optimization of DSP Algorithms

Fast Fixed-Point Optimization of DSP Algorithms

Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

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