Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Ahmadi, Majid; Zwoliński, Mark

doi:10.1109/iscas.2007.377976

Cited by 8 publications

(4 citation statements)

References 10 publications

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“…Four case studies were implemented with ST 0.12µm technology and applying this method in combination with the high level synthesis method and tools presented in [19] and Since, in practical implementations, there are pre-defined constraints which must be satisfied and therefore, other costs must be optimized with respect to them, an exhaustive set of synthesis optimizations were performed to show the design cost dependency on WL as a synthesis parameter along with the other classical synthesis parameters. Tables (3) to (6) show the optimization results for designs I to IV respectively.…”

Section: Resultsmentioning

confidence: 99%

Symbolic noise analysis approach to computational hardware optimization

Ahmadi

Zwoliński

2008

Proceedings of the 45th Annual Design Automation Conference

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This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.

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Section: Resultsmentioning

confidence: 99%

Symbolic noise analysis approach to computational hardware optimization

Ahmadi

Zwoliński

2008

Proceedings of the 45th Annual Design Automation Conference

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“…is is the first proposal where area and digital noise are objective functions. Additionally, the same authors propose an extension with a similar DFG-based methodology [85][86][87][88], but with power as an additional objective function. One of the most important contributions in this field was offered in [89], since they explained the use of a multichromosome approach, and consequently, it was more feasible to represent the scheduling and allocation tasks concurrently.…”

Section: Learning-based Methods Machine Learning Methods Have Been Used In Recent Yearsmentioning

confidence: 99%

“…e papers that used the most objective functions have been [86][87][88] dealing with four (considered to be a many-objectives optimization problem). In the case of the optimizations with HLS tools as a black box, the objective functions have been delay, area, power, and reliability because those are the ones that can be obtained from the software tools.…”

Section: Analysis Comparisons and Main Findingsmentioning

confidence: 99%

Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

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Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

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“…This model is able to minimize the overall interconnections of the resulting datapath. In [68] synthesis for datapath is discussed which is based on multiple-width shared bus architecture. This technique utilizes models of circuit area, delay, power consumption, and output noise which are related to functional unit grouping, binding, allocation, and different word-lengths.…”

Section: Considering Interconnect Area and Delaymentioning

confidence: 99%

Formal ESL Synthesis for Control-Intensive Applications

Dossis¹

2012

Advances in Software Engineering

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Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to automatically produce correct implementations from high-level, abstract, and executable specifications written in program code. If the HLS transformations that are applied on the source code are formal, then the generated implementation is correct-by-construction. The focus in this work is on application-specific design, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which is bound by the limits and constraints of the preexisting architecture. This work surveys and reviews past and current research in the area of ESL and HLS. Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process. The scheduler PARCS and the formal compilation of the system are tested with a number of benchmarks and real-world applications. This demonstrates the usability and applicability of the presented method.

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Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Cited by 8 publications

References 10 publications

Symbolic noise analysis approach to computational hardware optimization

Symbolic noise analysis approach to computational hardware optimization

Development of Multiobjective High-Level Synthesis for FPGAs

Formal ESL Synthesis for Control-Intensive Applications

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