Symbolic noise analysis approach to computational hardware optimization

Ahmadi, Arash; Zwoliński, Mark

doi:10.1145/1391469.1391573

Cited by 15 publications

(9 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is mostly based on noise energy analysis in the output, which is measured by error variance (r). In [28] we proposed a combined method in which a partially known quantity x is represented in a symbolic form as…”

Section: Applicationmentioning

confidence: 99%

“…These noise symbols are unknown symbolic variables in the range [À1 + 1] with a known PDF. This approach provides more accurate information about computational error at every point of the system, however it necessitates more computational effort during the optimization process [28]. This error analysis method requires the PDF of the computational error in the output of each computational unit in the hardware be known.…”

Section: Applicationmentioning

confidence: 99%

See 1 more Smart Citation

Fixed-point multiplication: A probabilistic bit-pattern view

Ahmadi

Zwoliński

2011

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Applicationmentioning

confidence: 99%

Section: Applicationmentioning

confidence: 99%

Fixed-point multiplication: A probabilistic bit-pattern view

Ahmadi

Zwoliński

2011

Microelectronics Reliability

View full text Add to dashboard Cite

“…Another way is to calculate a local disturbance error of the fidelity from the transformation and propagate that error across the entire design to obtain a global error estimate. Symbolic Noise Analysis (SNA) [12] can accomplish this task without simulation.…”

Section: A Algorithm Overviewmentioning

confidence: 99%

ColSpace: Towards algorithm/implementation co-optimization

Huang

Lach

2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

Abstract-Application-specific integrated circuits (ASICs) are physical implementations of algorithms, so implementation metrics are determined in large part by the algorithm specification. However, the system abstraction layers that have been developed to manage the ever-increasing complexity of digital systems separate algorithm designers from hardware designers, forcing the latter to work within the design space specified by the former, even for applications such as multimedia that do not have hard fidelity requirements. Designers typically employ informal iterative design to adjust fidelity, but a formal design methodology would increase designer efficiency and improve the quality of the solutions.This paper introduces such a methodology (and accompanying tool) that enables algorithm and implementation metrics to be co-optimized during early design exploration, opening the design space to include solutions that may provide, for example, significant performance improvements while only slightly compromising fidelity. Hierarchical dependency graphs (HDGs) are used to represent both the algorithm and the implementation architecture, providing a common interface through which algorithm designers and hardware designers can explore the collaborative space (ColSpace) together. Using the proposed technique, the ColSpace tool can trade off various metrics to find the best overall design while managing complexity with the HDG hierarchy. Two image processing case studies demonstrate that in ColSpace-optimized designs, latency savings can exceed fidelity losses, resulting in cost function reductions that would not have been possible without this co-optimization methodology.

show abstract

“…Another way is to calculate a local disturbance error of the fidelity from the transformation and propagate that error across the entire design to obtain a global error estimate. Symbolic Noise Analysis (SNA) [51] can accomplish this task without simulation.…”

Section: For Fidelity-compromising Transformationsmentioning

confidence: 99%

A Digital System Design Methodology for Efficient-Quality Tradeoffs Using Imprecise Hardware

Huang¹

View full text Add to dashboard Cite

High power consumption has become a major barrier in the design of modern applicationspecific integrated circuits (ASICs). Recent studies have demonstrated the potential for significant power reduction in ICs by allowing errors to occur during computation. While most existing techniques for achieving this rely on voltage-overscaling (VOS), it is only one example in the vast design space of Imprecise Hardware (IHW), which is capable of converting relaxed quality requirements into higher implementation efficiency.First we present the generalized concept of IHW, of which VOS is an example. A mathematical approach to IHW characterization is introduced to quantify error characteristics.We also present several novel IHW examples, including fidelity-compromising transformations at the algorithm level, imprecise adders and multipliers at the RTL level and the combined use of IHW and VOS.Since IHW expands the design space of traditional HW by one dimension (quality), it is imperative to develop a fast and accurate quality evaluation method to efficiently explore Thirdly, I want to thank my other committee members Prof.

show abstract

Symbolic noise analysis approach to computational hardware optimization

Cited by 15 publications

References 17 publications

Fixed-point multiplication: A probabilistic bit-pattern view

Fixed-point multiplication: A probabilistic bit-pattern view

ColSpace: Towards algorithm/implementation co-optimization

A Digital System Design Methodology for Efficient-Quality Tradeoffs Using Imprecise Hardware

Contact Info

Product

Resources

About