ColSpace: Towards algorithm/implementation co-optimization

Abstract

Abstract-Application-specific integrated circuits (ASICs) are physical implementations of algorithms, so implementation metrics are determined in large part by the algorithm specification. However, the system abstraction layers that have been developed to manage the ever-increasing complexity of digital systems separate algorithm designers from hardware designers, forcing the latter to work within the design space specified by the former, even for applications such as multimedia that do not have hard fidelity requirements. Designers typically employ informal iterative design to adjust fidelity, but a formal design methodology would increase designer efficiency and improve the quality of the solutions.This paper introduces such a methodology (and accompanying tool) that enables algorithm and implementation metrics to be co-optimized during early design exploration, opening the design space to include solutions that may provide, for example, significant performance improvements while only slightly compromising fidelity. Hierarchical dependency graphs (HDGs) are used to represent both the algorithm and the implementation architecture, providing a common interface through which algorithm designers and hardware designers can explore the collaborative space (ColSpace) together. Using the proposed technique, the ColSpace tool can trade off various metrics to find the best overall design while managing complexity with the HDG hierarchy. Two image processing case studies demonstrate that in ColSpace-optimized designs, latency savings can exceed fidelity losses, resulting in cost function reductions that would not have been possible without this co-optimization methodology.

Exploring the fidelity-efficiency design space using imprecise arithmetic

“…Multipliers [7], complex arithmetic operations [1], non-critical components of a color interpolation algorithm [8] and parallel execution cores [9] have all been subjects of imprecise design. Most of these imprecise circuits fall into either the FSM or ILM category and can thus be similarly analyzed.…”

“…Imprecise circuit components take advantage of this fidelity slack to provide performance and power benefits. Studies [1,2] have shown that significant power and delay savings over traditional "precise" designs can be achieved with acceptably small impact on the quality of results. Adding an extra metric of fidelity (a measure of result quality) to the design space adds another dimension to the optimal Pareto surface, the cross-sections of which reveal different (and usually better) tradeoff surfaces than in the original design space.…”

“…there is only one acceptable output vector resulting from a determined input vector) is over-constraining in many applications. As a result, many imprecise circuits (also known as unreliable circuits, fidelity-compromising components [1], stochastic processors [2], etc.) have been proposed to achieve solutions that surpass the Pareto bounds.…”

A Digital System Design Methodology for Efficient-Quality Tradeoffs Using Imprecise Hardware

“…(Table 2.2). [26] fidelity-compromising transformations [30] There is no widely accepted rule on which type of error will lead to higher output qual- …”

“…This section introduces a design optimization methodology through HDG manipulations that include fidelity-compromising transformations. A hierarchical depen- dency graph (HDG) [30] (Figure 4.1) is a data structure used to represent both the algorithm and its hardware implementation, enabling bi-directional communication between the algorithm and hardware designers during design space exploration. It shares some similarities with traditional task graphs [47][48][49] but is structured hierarchically to manage design com-plexity.…”