Exploring the fidelity-efficiency design space using imprecise arithmetic

Huang, Adam; Lach,

doi:10.1109/aspdac.2011.5722256

Cited by 19 publications

(14 citation statements)

References 11 publications

(17 reference statements)

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“…Soft additions are generally based on the operation of deterministic approximate logic or probabilistic imprecise arithmetic (categorized in [2] as design-time and run-time techniques). Two recently proposed adder architectures are representatives of these types.…”

Section: Introductionmentioning

confidence: 99%

On the Reliable Performance of Sequential Adders for Soft Computing

Liang

Han

Lombardi

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Addition is a significant operation in soft computing; several sequential adder designs have been proposed in the technical literature. These adders show different operational profiles; some of them are inspired by biological networks or the probabilistic nature of nanometric devices (such as the Lower-part OR Adder (LOA) and the Probabilistic Full Adder (PFA)). This paper deals with the reliability assessment and comparison of these sequential adder implementations. A new metric referred to as the mean error distance (MED) is proposed as a unified figure for evaluating the reliability of both probabilistic and deterministic adders. Reliability is analyzed using the so-called sequential probability transition matrices (S-PTMs) with respect also to error masking (as occurring due to the sequential nature of the addition process). A baseline sequential adder implementation, referred to as the Lower-bit Ignored Adder (LIA), is used as a benchmark for evaluating the other implementations. It is shown that compared with the LIA, the PFA has a better reliability at a small gate error rate, but at the cost of a larger overhead in area and therefore static power consumption. The LOA achieves a good tradeoff between reliability, area, power and delay compared to the LIA and PFA implementations.

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Section: Introductionmentioning

confidence: 99%

On the Reliable Performance of Sequential Adders for Soft Computing

Liang

Han

Lombardi

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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“…By contrast, analytical approaches are fast, but namic power savings from switching activity and voltage scalmost of them have limitations in supported approximation ing due to reduced logic complexity and critical path delays. We types [9, l3] or quality metrics [7,16]. The work in [ 13] in-demonstrate application of our quality-energy analysis to drive corperates a quality constraint in high-level synthesis, but only optimization of approximations over an entire DFG.…”

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confidence: 99%

Statistical quality modeling of approximate hardware

Lee

Han

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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Beyond traditional bit truncation, recently pro posed arithmetic and logic approximations have enriched the quality versus energy design space for custom hardware kernels in signal processing and other error-tolerant applications. Sys tematic exploration of such trade-offs requires fast, accurate, and generic quality-energy models that can drive datapath opti mizations. Existing quality estimation approaches, however, are either based on slow simulation or limited in supported approx imation types and quality metrics. In this paper, we propose a novel semi-analytical quality model that can predict a wide range of statistical metrics for arbitrary hardware approxima tions with deterministic error behavior. Input and error depen dencies are captured using one-time error-free simulation only. Combining our quality estimation with a faithful energy model considering both switching activity and voltage scaling, we pro vide a complete quality-energy optimization flow. Optimization results for FFT and IDCT benchmarks show that our approach is 28x faster than purely simulation-based exploration, and 2x faster than existing hybrid approaches, all while achieving com parable estimation accuracy.

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“…ER of the ETAIIM adder is given in Equation (8). N is the total bit width of the adder; bits-per-block (BPB) is the size of carry-look-ahead (CLA) blocks; k is the number of connected CLA blocks, an architectural parameter used to control error magnitudes.…”

Section: B Analysis For Computation Of Error Metricsmentioning

confidence: 99%

Statistical analysis and modeling for error composition in approximate computation circuits

Chan

Kahng

Kang

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-Aggressive requirements for low power and high performance in VLSI designs have led to increased interest in approximate computation. Approximate hardware modules can achieve improved energy efficiency compared to accurate hardware modules. While a number of previous works have proposed hardware modules for approximate arithmetic, these works focus on solitary approximate arithmetic operations. To utilize the benefit of approximate hardware modules, CAD tools should be able to quickly and accurately estimate the output quality of composed approximate designs. A previous work [10] proposes an interval-based approach for evaluating the output quality of certain approximate arithmetic designs. However, their approach uses sampled error distributions to store the characterization data of hardware, and its accuracy is limited by the number of intervals used during characterization.In this work, we propose an approach for output quality estimation of approximate designs that is based on a lookup table technique that characterizes the statistical properties of approximate hardwares and a regression-based technique for composing statistics to formulate output quality. These two techniques improve the speed and accuracy for several error metrics over a set of multiply-accumulator testcases. Compared to the interval-based modeling approach of [10], our approach for estimating output quality of approximate designs is 3.75× more accurate for comparable runtime on the testcases and achieves 8.4× runtime reduction for the error composition flow. We also demonstrate that our approach is applicable to general testcases.

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Exploring the fidelity-efficiency design space using imprecise arithmetic

Cited by 19 publications

References 11 publications

On the Reliable Performance of Sequential Adders for Soft Computing

On the Reliable Performance of Sequential Adders for Soft Computing

Statistical quality modeling of approximate hardware

Statistical analysis and modeling for error composition in approximate computation circuits

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