Performance study of a concurrent multithreaded processor

Tsai, Jeng‐Wei; Jiang, Zhenzhen; Ness, E.; Yew, Pen-Chung

doi:10.1109/hpca.1998.650543

Cited by 6 publications

References 20 publications

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The superthreaded processor architecture

Tsai

Huang

Amlo

et al. 1999

IEEE Trans. Comput.

123

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The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism available in general-purpose application programs. Unlike other CMAs that rely primarily on hardware for run-time dependence detection and speculation, the superthreaded processor combines compiler-directed thread-level speculation of control and data dependences with run-time data dependence verification hardware. This hybrid of a superscalar processor and a multiprocessor-ona-chip can utilize many of the existing compiler techniques used in traditional parallelizing compilers developed for multiprocessors. Additional unique compiler techniques, such as the conversion of data speculation into control speculation, are also introduced to generate the superthreaded code and to enhance the parallelism between threads. A detailed execution-driven simulator is used to evaluate the performance potential of this new architecture. It is found that a superthreaded processor can achieve good performance on complex application programs through this close coupling of compile-time and run-time information.

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The superthreaded processor architecture

Tsai

Huang

Amlo

et al. 1999

IEEE Trans. Comput.

123

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Extending value reuse to basic blocks with compiler support

Huang

Lilja

2000

IEEE Trans. Comput.

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Speculative execution and instruction reuse are two important strategies that have been investigated for improving processor performance. Value prediction at the instruction level has been introduced to allow even more aggressive speculation and reuse than previous techniques. This study suggests that using compiler support to extend value reuse to a coarser granularity than a single instruction, such as a basic block, may have substantial performance benefits. We investigate the input and output values of basic blocks and find that these values can be quite regular and predictable. For the SPEC benchmark programs evaluated, 90% of the basic blocks have fewer than 4 register inputs, 5 live register outputs, 4 memory inputs and 2 memory outputs. About 16% to 41% of all the basic blocks are simply repeating earlier calculations when the programs are compiled with the-O2 optimization level in the GCC compiler. Compiler optimizations, such as loop-unrolling and function inlining, affect the sizes of basic blocks, but have no significant or consistent impact on their value locality, nor the resulting performance. Based on these results, we evaluate the potential benefit of basic block reuse using a novel mechanism called the block history buffer. This mechanism records input and live output values of basic blocks to provide value reuse at the basic block level. Simulation results show that using a reasonably-sized block history buffer to provide basic block reuse in a 4-way issue superscalar processor can improve execution time for the tested SPEC programs by 1% to 14% with an overall average of 9% when using reasonable hardware assumptions.

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Using incorrect speculation to prefetch data in a concurrent multithreaded processor

Chen

Sendag

Lija

Proceedings International Parallel and Distributed Processing Symposium

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Performance study of a concurrent multithreaded processor

Cited by 6 publications

References 20 publications

The superthreaded processor architecture

The superthreaded processor architecture

Extending value reuse to basic blocks with compiler support

Using incorrect speculation to prefetch data in a concurrent multithreaded processor

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