Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94 1994
DOI: 10.1145/196244.196448
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Performance optimization using exact sensitization

Abstract: A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimization procedure that optimizes only sensitizable paths greater than . Unlike previous methods that use topological analysis only, this method accounts for both functional and topological interactions in the circuit. Comprehensive experimental results comparing the proposed technique to a state-of-the-art performance optimization proc… Show more

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Cited by 22 publications
(17 citation statements)
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References 14 publications
(30 reference statements)
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“…In the rest of this paper, the SPCF at y is denoted by Σy(Δy) for brevity. Traditionally, the SPCF has been used in timing-driven optimization during logic synthesis [26] and in variable latency designs [27]. Many algorithms for computing the SPCF have been proposed in literature.…”
Section: Definitionmentioning
confidence: 99%
“…In the rest of this paper, the SPCF at y is denoted by Σy(Δy) for brevity. Traditionally, the SPCF has been used in timing-driven optimization during logic synthesis [26] and in variable latency designs [27]. Many algorithms for computing the SPCF have been proposed in literature.…”
Section: Definitionmentioning
confidence: 99%
“…Logic restructuring with the goal of reducing delay of a mapped network has long been an important part of both technology independent [15] [2][10] [14] and technology dependent synthesis [8][11] [7] [4]. However, existing methods for delay-oriented logic restructuring have the following drawbacks:…”
Section: Introductionmentioning
confidence: 99%
“…A similar method was discussed in [2] and called the generalized select transform (GST) [10] [14]. This was used recently for timing optimization of sequential circuits [16].…”
Section: Introductionmentioning
confidence: 99%
“…Timing-driven optimization during multi-level logic synthesis is a well-researched area, and several solutions have been proposed in literature [1][2][3][4][5][6][7][8][9]. These techniques either restructure the critical paths or perform decomposition-based resynthesis of the circuit.…”
Section: Introductionmentioning
confidence: 99%
“…Restructuring techniques, such as [1][2][3][4], are computationally efficient but the improvements from these techniques are limited because restructuring is restricted to cutsets of nodes on the critical path. On the other hand, decomposition-based resynthesis techniques, such as [5][6][7], have immense scope for optimization because the space of possible transformations is vast. However, the algorithms proposed in literature are computationally intensive and the improvements achieved are limited by available computational resources.…”
Section: Introductionmentioning
confidence: 99%