Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND Flash memory error correction

Kim, Jonghong; Lee, Donghwan; Sung, Wonyong

doi:10.1109/icc.2012.6364973

Cited by 26 publications

(13 citation statements)

References 16 publications

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“…Errors in multi-level cell memories are mostly unidirectional and limited magnitude, because their dominant error sources, such as cell-to-cell interference and data retention errors, shift threshold voltage levels to either positive or negative side [1]. In addition, bidirectional errors are probable when these error sources have equivalent significance.…”

Section: Introductionmentioning

confidence: 99%

Codes Correcting Asymmetric/Unidirectional Errors along with Bidirectional Errors of Small Magnitude

Kotaki

Kitakami

2014

2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing

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Dominant error sources in multi-level cell NAND Flash memories shift threshold voltage levels to either positive or negative values, thus errors are modeled by nonbinary unidirectional channels. However, bidirectional errors can also be caused when positive and negative errors have equivalent significance. Compared to unidirectional cases, error magnitude of bidirectional errors are considered to be small. In this correspondence, novel error correcting codes which correct limited magnitude asymmetric/unidirectional errors along with bidirectional errors of relatively small magnitude are presented. They can be used to reduce encoding and decoding complexity compared to conventional symmetric error correcting codes.

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Section: Introductionmentioning

confidence: 99%

Codes Correcting Asymmetric/Unidirectional Errors along with Bidirectional Errors of Small Magnitude

Kotaki

Kitakami

2014

2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing

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“…Yet, these coding techniques are not powerful enough to significantly improve the system performance and call for stronger error correction schemes. To further improve the data integrity, soft-decision error correction codes are also used with flash memory such as LDPC codes where they have shown to outperform BCH coding scheme [11]- [13].…”

Section: Introductionmentioning

confidence: 99%

Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash

Aslam

Guan

Cai

2014

Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2014 Asia-Pacific

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NAND flash memory has been dominantly used in consumer electronic products ranging from hand-held phones to personal computers. However, the stored data in NAND flash memory is subject to several impairments such as Random Telegraph Noise (RTN), Cell-to-Cell Interference (CCI) and Data Retention Effect over time. In this paper, we focus on the RTN effect over flash memory cells which becomes even more serious as the memory approaches its lifetime. When the flash cells withstand increasingly large number of Program/Erase (P/E) operation, multiple interface traps are generated at tunnel oxide layer which results into large fluctuations in cell threshold voltage. These voltage fluctuations, in turn, degrade the system error performance. To tackle with this problem, we propose a simple yet effective system-level decoding scheme in which the memory cells are read multiple times to obtain threshold voltage fluctuations caused by RTN. Since each memory read operation produces a new realization of threshold voltage, we combine the read signal with LDPC extrinsic information. The performance improvements of our scheme are validated by computer simulation which shows that the lifetime of flash memory can be extended by more than 10K P/E cycles while maintaining bit-error-rate at 10´6 using NB-LDPC code over GF p4q with frame size N " 2272. This paper also presents the trade-off between performance improvement and extra memory sensing latency.

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“…We assume that the erased state (symbol 11) has a Gaussian distribution whose mean and standard deviation are 1.0 and 0.32 V, respectively, and the target programming voltages for the symbol 01, 00, and 10 are 2.6, 3.2, and 3.8 V, respectively. In order to generate the NAND Flash memory channel with different bit-error rates (BERs), we change the cell-to-cell coupling coefficient factor (CCF) [15,16]. The CCF primarily affects the variances of the threshold voltage distributions.…”

Section: Soft-decision Error Correcting Performance In Nand Flash Memorymentioning

confidence: 99%

“…In particular, in order to support soft-decision LDPC decoding, we adopt the LLR computation method proposed in [16], in which the four threshold voltage distributions are assumed as Gaussian distributions and the partial cumulative distribution functions of the Gaussian distribution are used [17] are a class of finitegeometry codes and show very low error-floor performance [18] as well as fast convergence speed [17], which are important properties for application to NAND Flash error correction.…”

Section: Soft-decision Error Correcting Performance In Nand Flash Memorymentioning

confidence: 99%

Low-energy error correction of NAND Flash memory through soft-decision decoding

Kim

Sung

2012

EURASIP J. Adv. Signal Process.

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The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.

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Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND Flash memory error correction

Cited by 26 publications

References 16 publications

Codes Correcting Asymmetric/Unidirectional Errors along with Bidirectional Errors of Small Magnitude

Codes Correcting Asymmetric/Unidirectional Errors along with Bidirectional Errors of Small Magnitude

Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash

Low-energy error correction of NAND Flash memory through soft-decision decoding

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