Performance of CMOS differential circuits

Ng, Pauline; Balsara, Poras T.; Steiss, D.

doi:10.1109/4.509871

Cited by 94 publications

(30 citation statements)

References 9 publications

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“…In order to quantify the amount of power saved, we use previously-reported research to estimate the amount of power that various functional units use [16,17,18]. From these sources we obtain power estimates assuming dynamic logic and relatively fast carry lookahead adders.…”

Section: Power Resultsmentioning

confidence: 99%

Dynamically exploiting narrow width operands to improve processor power and performance

Brooks

Martonosi

1999

Proceedings Fifth International Symposium on High-Performance Computer Architecture

223

177

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Section: Power Resultsmentioning

confidence: 99%

Dynamically exploiting narrow width operands to improve processor power and performance

Brooks

Martonosi

1999

Proceedings Fifth International Symposium on High-Performance Computer Architecture

223

177

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“…In order to quantify the amount of power saved, we use previously reported research to estimate the amount of power that various functional units use [Borah et al 1996;Ng et al 1996;Zimmermann and Fichtner 1997;Callaway and Swartzlander 1997]. From these sources we obtain power estimates assuming dynamic logic and relatively fast carry look-ahead adders.…”

Section: Power Results: Overviewmentioning

confidence: 99%

Value-based clock gating and operation packing

Brooks

Martonosi

2000

ACM Trans. Comput. Syst.

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The large address space needs of many current applications have pushed processor designs toward 64-bit word widths. Although full 64-bit addresses and operations are indeed sometimes needed, arithmetic operations on much smaller quantities are still more common. In fact, another instruction set trend has been the introduction of instructions geared toward subword operations on 16-bit quantities. For example, most major processors now include instruction set support for multimedia operations allowing parallel execution of several subword operations in the same ALU. This article presents our observations demonstrating that operations on "narrow-width" quantities are common not only in multimedia codes, but also in more general workloads. In fact, across the SPECint95 benchmarks, over half the integer operation executions require 16 bits or less. Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrow-width operations. The first, power-oriented optimization reduces processor power consumption by using operand-value-based clock gating to turn off portions of arithmetic units that will be unused by narrow-width operations. This optimization results in a 45%-60% reduction in the integer unit's power consumption for the SPECint95 and MediaBench benchmark suites. Applying this optimization to SPECfp95 benchmarks results in slightly smaller power reductions, but still seems warranted. These reductions in integer unit power consumption equate to a 5%-10% full-chip power savings. Our second, performance-oriented optimization improves processor performance by packing together narrow-width operations so that they share a single arithmetic unit. Conceptually similar to a dynamic form of MMX, this optimization offers speedups of 4.3%-6.2% for SPECint95 and 8.0%-10.4% for MediaBench. Overall, these optimizations highlight an increasing opportunity for value-based optimizations to improve both power and performance in current microprocessors.

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“…1, to get low-power and secure DPL implementations, in such a way the SABL solution could be overtaken either in performances or in security. For this purpose, after the characterization of several differential structures, we have selected the DPUN structure called Dynamic Differential Cascode Voltage Switch Logic (DDCVSL) [5], because of its relative simplicity.…”

Section: Proposed Implementationsmentioning

confidence: 99%

“…It is shown how commonly used differential logic gates can be enhaced for cryptographic applications. To achieve this objective, two methodologies are used together: one to improve the security in the DPDN [4] and other to achieve a low-power solution for the DPUN [5]. Making use of both methodologies, the performance of the differential logic gate is enhaced, achieving greater security against DPA attacks and reducing the power consumption and delay of the cell.…”

Section: Introductionmentioning

confidence: 99%

“…Making use of both methodologies, the performance of the differential logic gate is enhaced, achieving greater security against DPA attacks and reducing the power consumption and delay of the cell. The main contributions of this paper are: i) the optimization of the DPDN [4] to remove stored charge in internal nodes, trying to avoid harmful memory effects, ii) the spreading of DPA resistant feature to simpler DPUN [5], and iii) simulationbased DPA attacks to Sboxes (Substitution boxes) implemented with different proposals of Xor/Xnor and And/Nand gates, to assess the improvement of our proposals.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-Power Differential Logic Gates for DPA Resistant Circuits

Tena-Sánchez

Castro²,

Acosta

2014

2014 17th Euromicro Conference on Digital System Design

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Abstract-Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulationbased DPA attacks on Sbox9 are used to validate the effectiveness of the proposals.

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Performance of CMOS differential circuits

Cited by 94 publications

References 9 publications

Dynamically exploiting narrow width operands to improve processor power and performance

Dynamically exploiting narrow width operands to improve processor power and performance

Value-based clock gating and operation packing

Low-Power Differential Logic Gates for DPA Resistant Circuits

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