Low-Power Differential Logic Gates for DPA Resistant Circuits

Tena-Sánchez, Erica; Castro, Javier; Acosta, Antonio

doi:10.1109/dsd.2014.72

Cited by 4 publications

(8 citation statements)

References 6 publications

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Section: Evaluation and Resultsmentioning

confidence: 99%

“…In [15], [19], it was demonstrated that DPL-based DPA resistant gates are good candidates to replace CMOS counterparts for low-power secure systems against DPA attacks. This paper aims to demonstrate that additional countermeasures, as the ones presented in [8], [19] can also be implemented in TFET, with competitive security-cost trade-off. As a demonstrative vehicle we use the lightweight block cipher PRIDE [20], which uses a 64-bit input plaintext and a 128-bit key for the encryption in a total of 20 operation rounds.…”

Section: Evaluation and Resultsmentioning

confidence: 99%

“…• Classic: Classic SABL [7] implementation for a 65nm commercial technology from UMC foundry (UMC65) and its adaptation for TFETs [15]. • P: P modification for both XOR/XNOR and AND/NAND gates in UMC65 [8], [19] and its adaptation for TFETs presented in this work. • 2P: 2P modification for both XOR/XNOR and AND/NAND gates in UMC65 [8], [19] and its adaptation for TFETs presented in this work.…”

Section: Evaluation and Resultsmentioning

confidence: 99%

“…The design methodology of the optimized DPDN structure using TFET devices adapts the two approaches presented in [8] for CMOS technologies: i) equalizing the voltage values after evaluation phase in the internal nodes n1 and n2 using the single − switch (P) solution, and ii) setting the voltage value in n1 and n2 at the same V DD value using the double−switch (2P) solution [19]. In the adaptation to TFET technology, the single − switch solution (P) requires two transistors because of the characteristic unidirectionality of TFETs.…”

Section: Security Proposalmentioning

confidence: 99%

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Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

Delgado-Lozano¹,

Tena-Sánchez²,

Núñez³

et al. 2022

IEEE Embedded Syst. Lett.

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The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs.

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Section: Evaluation and Resultsmentioning

confidence: 99%

Section: Evaluation and Resultsmentioning

confidence: 99%

Section: Evaluation and Resultsmentioning

confidence: 99%

Section: Security Proposalmentioning

confidence: 99%

See 2 more Smart Citations

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

Delgado-Lozano¹,

Tena-Sánchez²,

Núñez³

et al. 2022

IEEE Embedded Syst. Lett.

Self Cite

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show abstract

“…To remedy the high power consumption produced by DPL solutions, there exist some solutions: i) using power-optimized circuit proposals, as the one presented in [44]; ii) making use of alternative architectures, as the adiabatic one in [45,46], iii) proposing new power-reduced DPL structures [47].…”

Section: Security Of Lightweight Cryptography Against Side-channel Attacksmentioning

confidence: 99%

Power and Energy Issues on Lightweight Cryptography

Acosta¹,

Tena-Sánchez²,

Jimenez-Fernandez³

et al. 2017

Journal of Low Power Electronics

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Portable devices as smartphones, smart cards and other embedded devices need encryption technology to guarantee security. Users store private data daily in electronic devices making use of cryptography to ensure data confidentiality, needing reliable authentication mechanisms. Typical encryption security is based on the usage of algorithms that are mathematically secure, but often requiring expensive computing and power resources. The implementation of security mechanisms on dedicated hardware has been shown as a first-order solution to achieve both required security and low power consumption with reduced resources, in the so-called lightweight cryptography. Upcoming Internet of Thing (IoT) is requiring such solutions extensively. Furthermore, the physical implementation of the encryption algorithm can leak side-channel information that can be used by an attacker to reveal secret key or private data. Therefore, the physical implementations of low-power cryptographic devices have to be carefully considered at algorithmic, circuit and layout levels, in order to be secure against active and passive attacks. A great effort has been recently devoted to the implementation of secure lightweight cryptography, occupying an increasingly large interest from academy and companies, to meet the challenges of IoT.The paper is a survey of i) lightweight cryptography algorithms; ii) techniques to reduce power applied to cryptohardware implementations; iii) vulnerability analysis of low-power techniques against side-channel attacks; and iv) the possibilities opened to emerging technologies and devices in the "More than Moore" scenario.

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Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Chong

Chen

et al. 2021

IEEE J. Emerg. Sel. Topics Circuits Syst.

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We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delayline control and a data-propagation control to amplify the dualhiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronouslogic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs.

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Low-Power Differential Logic Gates for DPA Resistant Circuits

Cited by 4 publications

References 6 publications

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

Power and Energy Issues on Lightweight Cryptography

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

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