Performance modeling of the interconnect structure of a 3-dimensionally integrated RISC-processor/cache-system

Abstract

In order to investigate the performance potential of 3-&mensionally integrated circuits for high performance computer systems a comparative study of the interconnect structure of a RISC-processor/cache system has been conducted. The impact of electrical parameters of interconnection lines as well as associated package parasitics on second level cache read access is investigated for 3-dimensionally integrated circuit structures and compared to conventional PCB-and advanced MCM-realizations of the system. Wiring dimensions and line drivers are optimized for the different packagmg technologies and optimal realizations are compared with respect to cache access time and power dissipation. Case studies show reductions of effective switching capacitances of more than an order of magnitude and reductions of second level cache access time of over 40% for optimized 3D-systems compared to conventional PCBrealizations.