VLSI design in the 3rd dimension

Strickland, Stephen A.; Ergin, Erhan; Kaeli, David; Zavracky, P.M.

doi:10.1016/s0167-9260(98)00006-6

Cited by 16 publications

(4 citation statements)

References 12 publications

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“…Under same conditions, simulations revealed resistivities of 3.45 cm and 3. 95 cm, for the semiglobal and local interconnects, respectively. It was also found that using any other less conformal barrier deposition technology such as ionized physical vapor deposition (IPVD) or collimated PVD (c-PVD), the resistivity values for local and semiglobal interconnects become higher than aluminum technology for the same dimensions, in about a decade.…”

Section: ) Simulation Of Surface Scattering and Barrier Thickness Efmentioning

confidence: 99%

“…However, with the growing menace of delay in recent times, this technology is being viewed as a potential alternative that can not only maintain chip performance well beyond the 130-nm node, but also inspire a new generation of circuit design concepts. Hence, there has been a renewed spur in research activities in 3-D technology [95]- [100] and their performance modeling [42], [67], [101]- [104].…”

Section: A Technology Optionsmentioning

confidence: 99%

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Banerjee¹,

Souri²,

Kapur³

et al. 2001

Proc. IEEE

900

411

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Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with especial attention to SoC design strategies. Finally, some of the promising technologies for manufacturing 3-D ICs have been outlined.

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Section: ) Simulation Of Surface Scattering and Barrier Thickness Efmentioning

confidence: 99%

Section: A Technology Optionsmentioning

confidence: 99%

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Banerjee¹,

Souri²,

Kapur³

et al. 2001

Proc. IEEE

900

411

View full text Add to dashboard Cite

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“…3D on-chip interconnection architectures have been investigated by a few researchers [4,7,24]. An NoC-Bus Hybrid structure for 3D interconnects was proposed in [7], and [4] proposed a dimensionally decomposed crossbar design for 3D NoCs.…”

Section: Noc Router Architecturesmentioning

confidence: 99%

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Park

Eachempati

Das

et al. 2008

2008 International Symposium on Computer Architecture

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Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. It can achieve up to 42% reduction in power consumption and up to 51% improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67% and 38%, respectively.

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“…Hence, it is extremely difficult to carry ICs further along the path of Moore's law beyond 32nm technologies. Recently, researchers have shown that scaling in the vertical dimension (i.e., 3D integration) can be a promising solution to mitigate interconnect delays and to put more functionality on the chip [Strickland et al 1998;Patti 2006]. In contrast to conventional 2D planar chips, this technique offers significant improvement in performance and reduction in power dissipation [Patti 2006].…”

Section: Introductionmentioning

confidence: 99%

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

Bansal²,

Ghosh

et al. 2008

J. Emerg. Technol. Comput. Syst.

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This article presents a holistic hybrid design methodology for low-power, low-cost, testable digital designs using low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). An alternate scaling rule under low thermal budget (due to flexible substrate) is developed to improve the performance of TFTs in the presence of process variation. We demonstrate that LTPS TFTs can be further optimized for ultralow-power subthreshold operation with performances comparable to contemporary single-crystal silicon-on-insulator (c-Si SOI) devices after process optimization. The optimized LTPS TFTs with high current drivability and less variability can comprise a promising low-cost option to augment Si CMOS technology, opening up a plethora of new hybrid 3D applications. We illustrate one such application: IC testing. Testing of complex VLSI systems is a prime concern due to design cost of DFT circuits, area/delay overheads, and poor test confidence. To harness the benefits of TFT technology, a novel low-power, process-tolerant, generic, and reconfigurable test structure designed using LTPS TFTs is proposed to reduce the test cost, as well as to improve diagnosability and verifiability, of complex VLSI systems. Due to proper optimization of TFT devices, the proposed test structure consumes low power but operates with reasonable performance. Furthermore, the test circuits do not consume any silicon area because they can be integrated on-chip using 3D technology. Since the test architecture is reconfigurable, this This research was supported by DARPA. 13:2• J. Li et al.eliminates the need to redesign built-in-self-test (BIST) components that may vary from one processor generation to another. We have developed test structures using 200nm TFT devices and evaluated them on designs implemented in 130nm bulk CMOS. For circuit simulations, we have developed a SPICE-compatible model for TFT devices. The BIST components designed using the test structures operate at 0.8-4.3 GHz (compared to 8.2 GHz in bulk CMOS) with low power consumption. The enhanced scan cells partially implemented in TFT (3D hybrid design) consume ∼24% less power and ∼15-20% less area of Si die compared to conventional bulk-Si design (2D planar design), with minimal delay overhead.

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VLSI design in the 3rd dimension

Cited by 16 publications

References 12 publications

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

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