An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

Abstract

This article presents a holistic hybrid design methodology for low-power, low-cost, testable digital designs using low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). An alternate scaling rule under low thermal budget (due to flexible substrate) is developed to improve the performance of TFTs in the presence of process variation. We demonstrate that LTPS TFTs can be further optimized for ultralow-power subthreshold operation with performances comparable to contemporary single-crystal silicon-on-insulator (c-Si SOI) devices after process optimization. The optimized LTPS TFTs with high current drivability and less variability can comprise a promising low-cost option to augment Si CMOS technology, opening up a plethora of new hybrid 3D applications. We illustrate one such application: IC testing. Testing of complex VLSI systems is a prime concern due to design cost of DFT circuits, area/delay overheads, and poor test confidence. To harness the benefits of TFT technology, a novel low-power, process-tolerant, generic, and reconfigurable test structure designed using LTPS TFTs is proposed to reduce the test cost, as well as to improve diagnosability and verifiability, of complex VLSI systems. Due to proper optimization of TFT devices, the proposed test structure consumes low power but operates with reasonable performance. Furthermore, the test circuits do not consume any silicon area because they can be integrated on-chip using 3D technology. Since the test architecture is reconfigurable, this This research was supported by DARPA. 13:2• J. Li et al.eliminates the need to redesign built-in-self-test (BIST) components that may vary from one processor generation to another. We have developed test structures using 200nm TFT devices and evaluated them on designs implemented in 130nm bulk CMOS. For circuit simulations, we have developed a SPICE-compatible model for TFT devices. The BIST components designed using the test structures operate at 0.8-4.3 GHz (compared to 8.2 GHz in bulk CMOS) with low power consumption. The enhanced scan cells partially implemented in TFT (3D hybrid design) consume ∼24% less power and ∼15-20% less area of Si die compared to conventional bulk-Si design (2D planar design), with minimal delay overhead.

17.4: Invited Paper: Characterization and Failure Analysis of OLED devices by FIB/TEM Techniques

“…As it is well recognized, in LTPS-TFT driven OELD device, it has been experimentally demonstrated and theoretically verified that the process integrity of LTPS channel layer has great impact to the performance of TFT performance, such the threshold voltage (Vth), Ion, which in turn affect the light emission of the associated OLED devices. [2,3] Many failure cases have been identified to be related to the LTPS process integrity, especially the polycrystalline structure of LTPS, such as number of defective grain boundaries associated with gran size, and size distribution of poly-Si, and LTPS layer thickness uniformity. It is well known that one of the key limiting factors for LTPS TFTs performance lies in the quality of LTPS layer, such as average grain size, layer uniformity.…”

“…Statistical variations induced by grain boundaries in LTPS are a major concern and are more significant than other parametric variations, like i.e., channel length and width, and oxide thickness. [3] For the failed device, the smaller grain sizes indicated the larger number of grain boundaries in the TFT layer. The defects, the trapping states correlated with the GBs not only affect Vt, but also carrier mobility i.e.…”