Creating 3D circuits using transferred films

Sailer, P.M.; Singhal, P.; Hopwood, Jeffrey; Kaeli, David; Zavracky, P.M.; Warner, K.; Vu, D.P.

doi:10.1109/101.646556

Cited by 16 publications

(7 citation statements)

References 6 publications

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“…Work [43,44]. The demonstration of a 3D ring oscillator and an imager with 3D integrated control electronics was a significant milestone for this approach.…”

Section: Wafer-level 3d Using Adhesive Bondingmentioning

confidence: 99%

Three‐Dimensional (3D) Integration

McMahon

Gutmann

2007

Microelectronic Applications of Chemical Mechanical Planarization

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Three-dimensional (3D) integration with interstrata vias has the potential of improving system performance while providing a platform for heterogeneous integration. Performance improvement in 3D integrated circuits (ICs) is mainly due to the reduction of interconnect length, which decreases interconnect delay and power consumption [1,2]. Small form factor is achieved in 3D ICs due to the stacking of active device layers one on top the other. A path for heterogeneous integration is realized if this stacking is done in a fashion that is back-end-of-line (BEOL) compatible, because interconnecting devices using fully fabricated wafers can reduce process incompatibilities.Approaches to 3D integration are often divided into die-level approaches and wafer-level approaches. Most often, the heterogeneous integration and small form factor advantages are obtained with die-level approaches; in addition, high performance and low manufacturing cost can be achieved with wafer-level approaches.CMP has permeated many aspects of IC processing but is particularly a dominant factor in BEOL interconnection. Copper damascene patterning has become the standard methodology for building a large number of interconnect layers in the vast majority of high-performance ICs. In 3D ICs, CMP is also critical in backside thinning, surface roughness reduction, and, in particular, feature topography control. Topography mitigation can particularly be a critical Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li

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“…Work [43,44]. The demonstration of a 3D ring oscillator and an imager with 3D integrated control electronics was a significant milestone for this approach.…”

Section: Wafer-level 3d Using Adhesive Bondingmentioning

confidence: 99%

Three‐Dimensional (3D) Integration

McMahon

Gutmann

2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…Low-temperature (< 450 0C) copper-copper or polyemide based wafer bonding can be used to bond two fully processed wafers for fabricating 3-D ICs [45,46,47]. In 3-D IC technology based on wafer bonding, after the fabrication of individual wafer, top wafer is attached to a handle wafer, and it is thinned down from the back side.…”

Section: O1mentioning

confidence: 99%

System-level performance evaluation of three-dimensional integrated circuits

Rahman¹,

Reif²

2000

IEEE Trans. VLSI Syst.

175

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As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies.Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3 rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% -50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.

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“…An straightforward extension of a 2D architecture [6] is found in the Rothko 3D architecture, which has routing-and-logic blocks (RLBs) placed in more than one layer [5]. Fine-grained interlayer connections were added outside each RLB, providing connections between cells above and below, using a specially designed technique [8], [9]. An improved version of Rothko architecturewhich advocates placing the routing in one layer and logic on another for more efficient layer utilization -appears in [7].…”

Section: Introductionmentioning

confidence: 99%

Exploring Potential Benefits of 3D FPGA Integration

Ababei

Maidee

Bazargan

2004

Field Programmable Logic and Application

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A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool, which will be available on the web for the research community, as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies have to offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. However, unlike the ASIC case, wire-length reduction does not automatically translate to much smaller circuit delays, unless multi-segment lengths are employed between layers. Our empirical analysis shows that wire-length can be reduced by up to 50% (20% on average) using 5 layers. Delay reductions are estimated to be up to 30% (15% on average) using the same number of layers.

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Creating 3D circuits using transferred films

Cited by 16 publications

References 6 publications

Three‐Dimensional (3D) Integration

Three‐Dimensional (3D) Integration

System-level performance evaluation of three-dimensional integrated circuits

Exploring Potential Benefits of 3D FPGA Integration

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