Performance improvement with circuit-level speculation

Liu, Tong; Lu, Shih-Lien

doi:10.1145/360128.360166

Cited by 46 publications

(36 citation statements)

References 41 publications

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“…Liu et al proposed a method that uses a register map cache (RMC) [31]. The RMC is smaller than the main RMT and can reduce its latency and energy consumption on a hit; however, its miss penalty may degrade performance.…”

Section: Related Workmentioning

confidence: 99%

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

Shioya

Ando

2016

IEICE Trans. Inf. & Syst.

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SUMMARYOut-of-order superscalar processors rename register numbers to remove false dependencies between instructions. A renaming logic for register renaming is a high-cost module in a superscalar processor, and it consumes considerable energy. A renamed trace cache (RTC) was proposed for reducing the energy consumption of a renaming logic. An RTC caches and reuses renamed operands, and thus, register renaming can be omitted on RTC hits. However, conventional RTCs suffer from several performance, energy consumption, and hardware overhead problems. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands that are short distance from producers outside traces, and solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead as compared to a conventional processor. key words: superscalar processor, register renaming, trace cache, energy efficiency

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Section: Related Workmentioning

confidence: 99%

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

Shioya

Ando

2016

IEICE Trans. Inf. & Syst.

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“…Speculative adders [1] exploit the fact that the typical carry propagation chain of an addition does not span the whole length of the adder, making it is possible to estimate an intermediate carry using a limited number of previous stages. Thus, the carry propagation chain, which is the critical path of the adder, can be split in two or more shorter paths, relaxing constraints over the entire design, reducing spurious glitching power, and improving the Energy-Delay-Area Product (EDAP) beyond the theoretical bounds of exact adders.…”

Section: Inexact Speculative Adder a Related Workmentioning

confidence: 99%

“…Inexact and approximate circuit design [1] is a radical approach to trade this counterproductive quest for perfection for substantial gains in power, speed, area and yield. The primary challenge, however, is to determine where and how to let an error or an approximation occur in the circuits without compromising the functionality or the user experience.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient inexact speculative adder with high performance and accuracy control

Camus

Schlachter

Enz

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. This paper presents a novel architecture of an Inexact Speculative Adder with optimized hardware efficiency and advanced compensation technique with either error correction or error reduction. This general topology of speculative adders improves performance and enables precise accuracy control. A brief design methodology and comparative study of this speculative adder are also presented herein, demonstrating power savings up to 26 % and energy-delay-area reductions up to 60 % at equivalent accuracy compared to the state-of-the-art. I. INTRODUCTIONAs mobile devices become ubiquitous, the power efficiency of digital systems has become a primary concern. Unfortunately, achieving low-power and Process-Voltage-Temperature (PVT) robustness requires complex and conflicting design constraints and safety margins. Typically, integrated circuits are designed to always ensure accurate operation. In order to avoid faulty results, they finish most computations earlier than the worstcase permitted delay or with more accuracy than needed for normal operation. This results in an inefficient use of resources and leads to "over-engineered" circuits.Inexact and approximate circuit design [1] is a radical approach to trade this counterproductive quest for perfection for substantial gains in power, speed, area and yield. The primary challenge, however, is to determine where and how to let an error or an approximation occur in the circuits without compromising the functionality or the user experience. With ever-increasing amount of data being processed, a wide variety of applications could tolerate inaccuracies. For example, in multimedia processing, a small proportion of errors is not perceptible to humans, and in highly computational algorithms such as data mining, search or recognition, the outcome is not required to be a single result but an adequate match. A promising approach to design inexact circuits is to use speculation to trade circuit accuracy for better power and speed. Taking advantage of such circuits would help to realize extremely energy-efficient and high-performance DSPs and hardware accelerators at lower integration cost and with higher speed, data rate or duty-cycling.The main contribution of this paper is to introduce a novel speculative adder: the Inexact Speculative Adder (ISA). The ISA improves performance, energy efficiency and error management through an optimized speculative path and with a versatile dual-direction error compensation technique. A brief design methodology is presented along with results and a comparative analysis of adder architectures.

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“…Circuit-Level Speculation [12] is a method introduced to reduce the critical path of the circuit using approximation, implementing only a portion of a circuit. The approximated implementation of the circuit is the most heavily used part of the original circuit based on simulation results.…”

Section: Circuit-level Speculationmentioning

confidence: 99%

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Crop

Krimer

Moezzi-Madani

et al. 2011

JLPEA

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While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.

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Performance improvement with circuit-level speculation

Cited by 46 publications

References 41 publications

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

Energy-efficient inexact speculative adder with high performance and accuracy control

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

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