Performance-driven syntax-directed synthesis of asynchronous processors

Abstract

The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthesis paradigm that compiles transparently a system specification written in a high-level language into a network of pre-designed handshaking modules. The transparency is provided by a one-to-one mapping from language constructs to the module networks that implement them. This gives the designer flexibility, at the language level, to optimise the resulting circuit in terms of performance, area or power.This paper introduces new techniques that exploit this flexibility to improve the performance of synthesised asynchronous systems. The results of a series of transistor level simulations show that these techniques, combined with optimised handshake module implementations, can produce close to a ten-fold improvement in the performance of a 32-bit, ARM-compatible, asynchronous processor used in an experimental smartcard SoC, without introducing any changes to the original processor architecture.

Teak: A Token-Flow Implementation for the Balsa Language

“…The results shown here are for fixed-gate delay, gatelevel simulation. For the Balsa circuits, all performancedriven optimisations described in [13] were applied. Teak circuits are produced by compiling Balsa language descriptions with the 'teak'compiler, producing component netlists which are then expanded into gate-level netlists using 'balsanetlist' from the Balsa system.…”

“…Consider the following segment of code which is a simplified version of a 'sign adjust' unit for the multiplicand input of the Booth multiplier in the nanoSpa processor [13] [14]. The circuit takes an N bit input word b and, depending of the type of multiplication specified by the mType The resulting circuit is shown in Fig.…”

Description-Level Optimisation of Synthesisable Asynchronous Circuits

“…In particular, true asynchronous operation of the system pipeline, a data-driven coding style are presented as performance-driven description techniques [6].…”

“…The optimisations presented here were evaluated using the following design examples: (i) the 32-bit nanoSpa processor core [6], (ii) a Viterbi decoder (VD), (iii) a channel-sliced wormhole router [17]. All results were obtained for prelayout, transistor-level simulations, using a 180nm technology cell library.…”

“…• Component optimisation: this is based on finding alternative designs for the handshake components that result in more concurrent, faster operation [6]. An orthogonal alternative to the above is to exploit the directness of the synthesis method at the description level.…”