Teak: A Token-Flow Implementation for the Balsa Language

Abstract

Abstract-This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise handshake interleaving and enclosure by separating out control 'go' and 'done' signalling into separate channels rather than using different phases of the asynchronous handshake. This leads to circuits in which optimisation and control overhead mitigation can be carried out by merging/separating control and data channels and by introducing handshake-decoupling latches. This work aims to make Balsa descriptions implementable in the more widely used and understood higher performance token-based asynchronous circuit styles.

Structure-Based Deadlock Checking of Asynchronous Circuits

“…Assuming no conflicts while doing the data reading and writing, we treat each Variable read or write as an Operator component. Very big asynchronous circuits can be designed using Teak [17] . Simulation can be used to verify the correct functionality of these circuits.…”

“…To the best of our knowledge, this work is the first to address the idea that a Steer-Merge bundle is not slack-elastic. As an application, the method derived is used to verify the deadlock-freeness of the circuits generated by a syntax-directed asynchronous design tool -Teak [17] , which is a data-driven implementation of Balsa [1] . Although we simplify the deadlock checking problem by considering only acyclic component networks, it is revealed that the While and Loop structures in Teak can still be handled in a series of steps that breaks the channel cycles and then checks to see if it is well-formed.…”

Uncle - An RTL Approach to Asynchronous Design

“…This section presents Greatest Common Denominator (GCD) and Viterbi decoder design examples and compares them to Balsa-generated designs, as that allows direct complete-system comparisons (Teak [13][16], a successor to Balsa, will be discussed at the end of this section). There have been other toolsets that have addressed parts of the NCL asynchronous dual-rail synthesis problem, such as ATN [11] (combinational logic only, dual-rail expansion, timing-driven relaxation, technology mapping) and the toolset used by Theseus Logic [15] in 1995-2005 (roughly) timeframe (automated combinational logic only, ack networks manually created, synthesis using Synopsys); also had cell merging, and a simulator with orphan detection.…”

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA

“…The community has attempted to address performance issues by improving the control flow [6], [7], [8]. Recently, Teak [9] and Click [10] have been proposed as dataflow synthesis frameworks to tackle the control overhead of Balsa and Haste, respectively.…”