Automatic Compilation of Data-Driven Circuits

Taylor, Sam; Edwards, Doug; Plana, Luis A.

doi:10.1109/async.2008.14

Cited by 11 publications

(5 citation statements)

References 16 publications

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“…The data-driven style of our handshake circuits is very similar (i.e. passive inputs, active outputs) and is based on the same insights as in the work of Taylor for Balsa [1], [2], [3]. Taylor has chosen for a datadriven subset of Balsa, which is then compiled in a syntaxdirected way into a data-flow circuit.…”

Section: Discussionmentioning

confidence: 99%

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Click Elements: An Implementation Style for Data-Driven Compilation

Peeters

Beest

Wit

et al. 2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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This paper presents a new design template and design flow for the implementation of data-driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only storage elements, not only for the datapaths, but also for the control circuits; latches and C-elements that are common in many asynchronous circuit design styles are not required. The design template uses a two-phase handshake protocol for inter-component communication. In a pipeline structure, these circuits operate near the speed of Mousetrap circuits, but the required design-flow is simpler. The implementation stylewhich we refer to as Click elements -has been chosen to resemble synchronous circuits as much as possible. This allows for the use of conventional optimization and timing tools in the design flow and for a cheaper design-for-test implementation. The click templates are well suited for a data-flow driven compilation flow, which avoids much of the control overhead of traditional syntax-directed compilation. The two-phase circuits show a significant improvement in performance and energy efficiency compared to four-phase single-rail circuits.

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Section: Discussionmentioning

confidence: 99%

“…Dataflow techniques are well known in compiler design and are now rapidly gaining popularity in asynchronous circuit design [1], [2], [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Click Elements: An Implementation Style for Data-Driven Compilation

Peeters

Beest

Wit

et al. 2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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“…The circuit generated by Balsa is control driven [11]. Data paths are synchronized by control circuits, therefore, the size of glue logic between data path and control logic, such as the MUX, DEMUX and read control of variables, are linear with the wire count of data paths.…”

Section: A Hardware Implementationmentioning

confidence: 99%

Building asynchronous routers with independent sub-channels

Song

Edwards

2009

2009 International Symposium on System-on-Chip

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Abstract-Network-on-chip (NoC) has been used as the new onchip communication paradigm. Asynchronous NoCs are power efficient and robust to process variation but they are slow. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element and buffer trees introduced by the synchronization increase the cycle period. A new router is proposed to use multiple independent sub-channels to transmit data. Since the synchronization is removed, the cycle period of all sub-channels are reduced speeding up the network. Two routers, one using multiple independent sub-channels and one using the synchronized wide channel, are implemented at the layout level. The simulation results show that the new router using multiple independent sub-channels reduces the router latency and the cycle period.

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“…In order to enable higher speed it is necessary to support a data-driven pipelined design style as well. Research at the University of Manchester [20] has addressed this by extending the Balsa language with constructs that will allow a designer to express data-flow. This must be supported by a set of data-flow handshake-components such as combinatorial circuit blocks and variables, both with passive input ports and active output ports, such that controlless data-driven pipelined circuits may be generated.…”

Section: Data-driven Circuitsmentioning

confidence: 99%

Current trends in high-level synthesis of asynchronous circuits

Sparsø

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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Abstract-This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e.g. the Haste/TiDE tool from Handshake Solutions or the Balsa tool from the University of Manchester. The aims are to add highlevel synthesis capabilities to these tools and to extend the tools such that a wider range of (higher speed) micro-architectures can be generated. Another branch of research takes a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly continuoustime asynchronous circuits that operate without a clock. The perspective here is that the substitution/conversion is done as the final step in an otherwise conventional synchronous design flow.

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Automatic Compilation of Data-Driven Circuits

Cited by 11 publications

References 16 publications

Click Elements: An Implementation Style for Data-Driven Compilation

Click Elements: An Implementation Style for Data-Driven Compilation

Building asynchronous routers with independent sub-channels

Current trends in high-level synthesis of asynchronous circuits

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