Building asynchronous routers with independent sub-channels

Abstract

Abstract-Network-on-chip (NoC) has been used as the new onchip communication paradigm. Asynchronous NoCs are power efficient and robust to process variation but they are slow. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element and buffer trees introduced by the synchronization increase the cycle period. A new router is proposed to use multiple independent sub-channels to transmit data. Since the synchronization is removed, the cycle period of all sub-channels are reduced speeding up the network. Two routers, one using multiple independent sub-channels and one using the synchronized wide channel, are implemented at the layout level. The simulation results show that the new router using multiple independent sub-channels reduces the router latency and the cycle period.

Description-Level Optimisation of Synthesisable Asynchronous Circuits

“…Consider the example code in figure 10 adapted from the description of the input buffer of a sliced-channel wormhole router designed in Balsa [17]. The first value received at input d_in[0] is the header flit.…”

“…The destination is chosen accordingly to the comparisons and the order of priority specified in the description. --data transfer commands omitted |0b001 then sync req [WEST] --data transfer commands omitted else sync req [LOCAL] --data transfer commands omitted end end end end Figure 11: Optimised, simplified description of the South input buffer of a sliced-channel wormhole router [17].…”

“…The optimisations presented here were evaluated using the following design examples: (i) the 32-bit nanoSpa processor core [6], (ii) a Viterbi decoder (VD), (iii) a channel-sliced wormhole router [17]. All results were obtained for prelayout, transistor-level simulations, using a 180nm technology cell library.…”