Performance characteristics of the Cray X1 and their implications for application performance tuning

Shan, Hongzhang; Strohmaier, Erich

doi:10.1145/1006209.1006235

Cited by 10 publications

(6 citation statements)

References 12 publications

(9 reference statements)

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“…As a result, the systems can achieve a high sustained performance. However, although the performance of the whole system has been evaluated, the performance gain due to ECache is not quantitatively discussed [10] [11].…”

Section: Related Work 21 Cache Memory For Vector Processorsmentioning

confidence: 99%

“…A cache memory for vector processors has been so far employed by modern vector processors such as Cray X1 and NEC SX-9 [3] [12]. Although the performance of vector supercomputers with a cache has already been reported [4][10] [11], the performance gain due to the cache is not quantitatively examined yet. To realize efficient large-scale simulations on the modern vector supercomputers, one important issue is about the optimization techniques to exploit the limited size of cache memory.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Performance tuning and analysis of future vector processors based on the roofline model

Sato

Nagaoka

Musa³

et al. 2009

Proceedings of the 10th Workshop on MEmory Performance: DEaling With Applications, Systems and Architecture

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Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, an on-chip vector cache mechanism is promising for the vector processors. Although the effectiveness of the vector cache has been evaluated, cache-conscious tuning of vector codes and the analysis of the obtained performance have not been discussed yet. Under this situation, the purpose of this paper is to establish a strategy for performance tuning of a vector processor with a cache to exploit its potential. To analyze its sustained performance, this paper uses the roofline model. Several optimization techniques are applied to real scientific and engineering applications, and their effects are assessed with the model. We confirm that the model can guide users to effective tuning so as to maximize its gain. We also discuss the energy efficiency of the on-chip vector cache.

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Section: Related Work 21 Cache Memory For Vector Processorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance tuning and analysis of future vector processors based on the roofline model

Sato

Nagaoka

Musa³

et al. 2009

Proceedings of the 10th Workshop on MEmory Performance: DEaling With Applications, Systems and Architecture

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“…APEX-Map [2][3][4]22,23] is a tunable synthetic benchmark that measures global data access performance. It is designed based on parameterized concepts for temporal and spatial locality and generates a global data access stream according to specified levels of these measures of locality.…”

Section: Data Locality Concepts and Application Performance Charactermentioning

confidence: 99%

APEX‐Map: a parameterized scalable memory access probe for high‐performance computing systems

Strohmaier

Shan

2007

Concurrency and Computation

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SUMMARYThe memory wall between the peak performance of microprocessors and their memory performance has become the prominent performance bottleneck for many scientific application codes. New benchmarks measuring data access speeds locally and globally in a variety of different ways are needed to explore the ever increasing diversity of architectures for high-performance computing. In this paper, we introduce a novel benchmark, APEX-Map, which focuses on global data movement and measures how fast global data can be fed into computational units. APEX-Map is a parameterized, synthetic performance probe and integrates concepts for temporal and spatial locality into its design. Our first parallel implementation in MPI and various results obtained with it are discussed in detail. By measuring the APEX-Map performance with parameter sweeps for a whole range of temporal and spatial localities performance surfaces can be generated. These surfaces are ideally suited to study the characteristics of the computational platforms and are useful for performance comparison. Results on a global-memory vector platform and distributed-memory superscalar platforms clearly reflect the design differences between these different architectures.

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“…The X1 provides a large set of registers to reduce the number of memory accesses, reduce register spills, eliminate write-afterread dependencies and hide memory latency. The register set includes thirty-two 64-bit vector registers, 8 Fig. 1.…”

Section: Processing Node Architecturementioning

confidence: 99%

“…Cray X1 optimization strategies have been reported for a set of synthetic benchmarks [8]. In this paper, we conduct performance and scaling analysis of a scientific application called Parallel Ocean Program (POP), which was developed at the Los Alamos National Laboratory [13].…”

Section: Applicationmentioning

confidence: 99%

Performance and Scalability Analysis of Cray X1 Vectorization and Multistreaming Optimization

Alam

Vetter

2005

Lecture Notes in Computer Science

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Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hardware resources and its high memory bandwidth. A Cray X1 node is composed of four MSPs, which in turn are composed of four single streaming processors (SSP). Each SSP contains a superscalar processing unit and two vector processing units. Compiler vectorization provides loop level parallelization and uses the vector processing hardware. Multistreaming code generation by the compiler permits execution across the SSPs of an MSP on a block of code. In this paper, we analyze overall impact of loop-level compiler optimization on a scientific application called Parallel Ocean Program (POP). POP has been extensively optimized for X1 by instrumenting the code using X1 compiler directives. We compare and contrast automatic and manual optimization schemes available on X1 and analyze their impact on the code performance and scalability. Our results show that the addition of compiler directives increases the average vector length, thereby improving the single node performance significantly. However, this code scales at a slower rate as the local workload volume decreases and the communication costs increase.

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Performance characteristics of the Cray X1 and their implications for application performance tuning

Cited by 10 publications

References 12 publications

Performance tuning and analysis of future vector processors based on the roofline model

Performance tuning and analysis of future vector processors based on the roofline model

APEX‐Map: a parameterized scalable memory access probe for high‐performance computing systems

Performance and Scalability Analysis of Cray X1 Vectorization and Multistreaming Optimization

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