2007
DOI: 10.1002/cpe.1166
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APEX‐Map: a parameterized scalable memory access probe for high‐performance computing systems

Abstract: SUMMARYThe memory wall between the peak performance of microprocessors and their memory performance has become the prominent performance bottleneck for many scientific application codes. New benchmarks measuring data access speeds locally and globally in a variety of different ways are needed to explore the ever increasing diversity of architectures for high-performance computing. In this paper, we introduce a novel benchmark, APEX-Map, which focuses on global data movement and measures how fast global data ca… Show more

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Cited by 5 publications
(4 citation statements)
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References 11 publications
(18 reference statements)
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“…Denning surveyed analytical models of locality [1]. Recently, Ibrahim and Strohmaier uses an analytical model in APEX-Map for analyzing the miss rate curve [3,5]. Ding and Zhong [2] used linear fitting to find the correlation between the input size and the reuse distance.…”
Section: Benefits From Footprint Curve Fittingmentioning
confidence: 99%
“…Denning surveyed analytical models of locality [1]. Recently, Ibrahim and Strohmaier uses an analytical model in APEX-Map for analyzing the miss rate curve [3,5]. Ding and Zhong [2] used linear fitting to find the correlation between the input size and the reuse distance.…”
Section: Benefits From Footprint Curve Fittingmentioning
confidence: 99%
“…A number of approaches have been proposed to generating shared cache MRCs [15,[28][29][30][31][32][33]. The common technique using these approaches is to calculate the LRU stack distance (also called reuse distance) which is first proposed by Mattson et al [15].…”
Section: A Generating Mrcsmentioning
confidence: 99%
“…A variety of schemes or models thus have been created to reduce this overhead. Ibrahim et al presented a mathematical equation to describe the relation between their Apex-Map framework [32] and reuse distance distributions [33]. To compute a reuse distance distribution, this approach needs to use Valgrind to collect the memory trace of the code of interest, which still incurs high runtime overhead and storage cost.…”
Section: A Generating Mrcsmentioning
confidence: 99%
“…Therefore, the initial step of our studies is the analysis of memory access patterns of application's phases, and the subsequent creation of a synthetic tunable probe that could mimic this memory pattern. Both [18] and [20] are different approaches of the development of a synthetic probe that can represent memory access. We aim to create a probe who is able to represent not only the memory access precisely, but as well to mimic another factors important to represent the performance of an application.…”
Section: Next Stepsmentioning
confidence: 99%