Performance tuning and analysis of future vector processors based on the roofline model

Abstract

Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, an on-chip vector cache mechanism is promising for the vector processors. Although the effectiveness of the vector cache has been evaluated, cache-conscious tuning of vector codes and the analysis of the obtained performance have not been discussed yet. Under this situation, the purpose of this paper is to establish a strategy for performance tuning of a vector processor with a cache to exploit its potential. To analyze its sustained performance, this paper uses the roofline model. Several optimization techniques are applied to real scientific and engineering applications, and their effects are assessed with the model. We confirm that the model can guide users to effective tuning so as to maximize its gain. We also discuss the energy efficiency of the on-chip vector cache.

Cache-aware Roofline model: Upgrading the loft

“…In particular, the Roofline model [10] provides insights into inherent architectural bottlenecks and potential application optimizations. Its usefulness is patent in several works [9], both at the application [4], [6], [8] and at the architectural level [5], [7].…”

Performance prediction of finite-difference solvers for different computer architectures

“…This model has been applied to reallife codes in the past to analyze and report performance including oceanic climate models [5], combustion modeling [6] and even seismic imaging [7]. It has also been used to evaluate the effectiveness of implementation-time optimizations like autotuning [8], or cache-blocking on specific hardware platforms like vector processors [9] and GPUs [10]. Tools are available to plot the machine-specific parameters of the roofline model automatically [11].…”

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

“…The roofline model [1], proposed in 2008, is a visual performance model that makes the identification of potential bottlenecks easier and provides a guideline to explore the architecture. It has been proved to be flexible enough to characterize not only multicore architectures but also innovative architectures ( [2][3][4]). In the GPU community the model has been well accepted ( [5][6][7]), due to the similarity of GPU architectures and multicore processors.…”