Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs

Abstract

Physical(ly) Unclonable Functions (PUFs) are expected to represent a solution for secure ID generation, authentication, and other important security applications. Researchers have developed several kinds of PUFs and self-evaluated them to demonstrate their advantages. However, both performance and security aspects of some proposals have not been thoroughly and independently evaluated. Third-party evaluation is important to discuss whether a proposal performs according to what the developers claim, regardless of any accidental bias. In this paper, we focus on Glitch PUFs (GPUFs) that use an AES S-Box implementation as a glitch generator, as proposed by Suzuki et al. [1]. They claim that this GPUF is one of the most practically feasible and secure delay-based PUFs. However, it has not been evaluated by other researchers yet. We evaluate GPUFs implemented on FPGAs and present three novel results. First, we clarify that the total number of challenge-response pairs of GPUFs is 2 19 , instead of 2 11. Second, we show that a GPUF implementation has low robustness against voltage variation. Third, we point out that the GPUF has "weak" challenges leading to responses that can be more easily predictable than others by an adversary. Our results indicate that GPUFs that use the AES S-Box as the glitch generator present almost no PUF-behavior as both reliability and uniqueness are relatively low. In conclusion, our case study on FPGAs suggests that GPUFs should not use the AES S-Box as a glitch generator due to performance and security reasons.

Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis

“…Hence these three NOR gates are predicted to be influential NOR gates, i.e. (enforced bit, enforced value)= (58, 1), (13,0), (6,1). Table II also shows the 6 patterns of influential NOR gates for each m. From Table II, we see that more than 65% of responses become 1 in the BR-PUF with just one influential NOR gate (i.e.…”

“…This approach prevents a leakage of the key outside, and makes it impossible to counterfeit things. However, recent research has found that the secret key could be revealed by de-packaging The preliminary version of this paper was presented in a Japanese domestic symposium without peer review [1].…”

Lightweight Security Protocol for WiSense based Wireless Sensor Network

“…Each round of encryption uses the following processes viz. SubBytes, ShiftRows, MixColumns and AddRoundKey [17]. There are in total ten rounds with the last round skipping the MixColumns step.…”

“…Each 16 bytes in the block needs to processed separately and in parallel for the substation. However, for practical applications this would cause to 16 copies of the S-Box to be present for a single round itself and for a full pipeline implementation, 160 copies of the S-Box table for the entire encryption process [17]. A total of 40960 bytes of memory would be needed for the SubBytes step alone, which is expensive in sensor nodes.…”

Uniquely Identifiable Tamper-Evident Device Using Coupling between Subwavelength Gratings

“…(1) Glitch PUFs relying on delays, use glitches in combinatorial logic circuits [157][158][159][160].…”