Electronic devices may undergo attacks going beyond traditional cryptanalysis. Side-channel analysis (SCA) is an alternative attack that exploits information leaking from physical implementations of e.g. cryptographic devices to discover cryptographic keys or other secrets. This work comprehensively investigates the application of a machine learning technique in SCA. The considered technique is a powerful kernel-based learning algorithm: the Least Squares Support Vector Machine (LS-SVM). The chosen side-channel is the power consumption and the target is a software implementation of the Advanced Encryption Standard. In this study, the LS-SVM technique is compared to Template Attacks. The results show that the choice of parameters of the machine learning technique strongly impacts the performance of the classification. In contrast, the number of power traces and time instants does not influence the results in the same proportion. This effect can be attributed to the usage of data sets with straightforward Hamming weight leakages in this first study.

Arbiter Physically Unclonable Functions (PUFs) have been proposed as efficient hardware security primitives for generating device-unique authentication responses and cryptographic keys. However, the assumed possibility of modeling their underlying challenge-response behavior causes uncertainty about their actual applicability. In this work, we apply wellknown machine learning techniques on challenge-response pairs (CRPs) from 64-stage Arbiter PUFs realized in 65nm CMOS, in order to evaluate the effectiveness of such modeling attacks on a modern silicon implementation. We show that a 90%-accurate model can be built from a training set of merely 500 CRPs, and that 5000 CRPs are sufficient to perfectly model the PUFs.To study the implications of these attacks, there is need for a new methodology to assess the security of PUFs suffering from modeling. We propose such a methodology and apply it to our machine learning results, yielding strict bounds on the usability of Arbiter PUFs. We conclude that plain 64-stage Arbiter PUFs are not secure for challenge-response authentication, and the number of extractable secret key bits is limited to at most 600.

Physical(ly) Unclonable Functions (PUFs) are expected to represent a solution for secure ID generation, authentication, and other important security applications. Researchers have developed several kinds of PUFs and self-evaluated them to demonstrate their advantages. However, both performance and security aspects of some proposals have not been thoroughly and independently evaluated. Third-party evaluation is important to discuss whether a proposal performs according to what the developers claim, regardless of any accidental bias. In this paper, we focus on Glitch PUFs (GPUFs) that use an AES S-Box implementation as a glitch generator, as proposed by Suzuki et al. [1]. They claim that this GPUF is one of the most practically feasible and secure delay-based PUFs. However, it has not been evaluated by other researchers yet. We evaluate GPUFs implemented on FPGAs and present three novel results. First, we clarify that the total number of challenge-response pairs of GPUFs is 2 19 , instead of 2 11. Second, we show that a GPUF implementation has low robustness against voltage variation. Third, we point out that the GPUF has "weak" challenges leading to responses that can be more easily predictable than others by an adversary. Our results indicate that GPUFs that use the AES S-Box as the glitch generator present almost no PUF-behavior as both reliability and uniqueness are relatively low. In conclusion, our case study on FPGAs suggests that GPUFs should not use the AES S-Box as a glitch generator due to performance and security reasons.