Performance Analysis of Sub 10 nm Double Gate Circular MOSFET

Sagar, Kallepelli; Maheshwaram, Satish

doi:10.1007/s12633-022-01668-w

Cited by 5 publications

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“…26,27 A circular double gate transistor (CDGT) has recently been proposed, which provides better electrical performance than CGT at lower technology nodes. 28,29 With the advantages of both NSH-FETs and Circular geometry, in this work, a new idea called Circular Nanosheet FETs (C-NSFETs) is proposed at sub 10 nm channel length with an internal silicon pad as a drain. Further, we expand our work in terms of stacked C-NSFETs like 2 sheets, 3 sheets, and 4 sheets and compare their electrical performance for both N-type& P-type MOSFETs.…”

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A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

Sagar

Maheshwaram

2022

ECS J. Solid State Sci. Technol.

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Nanosheet metal oxide semiconductor field effect transistors (MOSFETs) with circular layout geometry, i.e. circular nanosheet MOSFETs (C-NSFETs) were explored using fully calibrated TCAD for high-performance (HP) applications at 10 nm gate length. The DC parameters such as drive current (ION), leakage current (IOFF), ON/OFF current ratio, Subthreshold slope (SS), and Drain-induced-barrier lowering (DIBL) are extracted. Further, we analyzed the behavior of C-NSFETs by vertically stacking the number of sheets (2-sheet, 3-sheet, and 4-sheet) and named stacked circular nanosheet MOSFETs and also compared the variations of their DC FOMs (figures of merit), is observed that the device drive current level is further improving by stacking of multiple Nanosheets within the same foot-print. The drive current of the device with the stacking of 4 sheets has an improvement of ~ 4 times when compared to single sheet C-NSFET.

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