TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications

Varma, Srinivas; Chowdari, Ch. Pratyusha; Jayanthi, D; Panigrahy, Asisa Kumar; Jamal, K

doi:10.1109/icccnt54827.2022.9984597

Cited by 1 publication

(1 citation statement)

References 19 publications

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“…New circuitry was added to the design of the original comparator, which helps to speed up the active comparator at low-level supply voltages [6][7][8][9].Four different three-stage comparator circuit topologies have been compared in this paper. Circuits with and without lector methods, three-stage comparator circuits, and altered variations of these circuits are also included in the comparison [10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Implementation of three stage comparator using a modified latch with sustainable resources

Navya,

Jamal,

Valiveti

et al. 2023

E3S Web Conf.

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In this paper, the current study uses a lector technique to modify the latch. The Lector approach is one of the top low-power methods for IC technologies. The locking mechanism is the third stage in our proposed design for a three-stage comparator. The lector approach is used for the three-stage comparator circuit in this case and its modified version. Pre-amplifier stages are the first two levels. The improved performance of this comparator circuit uses two sets of complementary biased two-stage preamplifiers. The traditional three-stage amplifier decreased the latency, while the modified version of the modified three-stage amplifier focused on the kickback noise. The proposed design of this three-stage comparator, which employs a lector approach, concentrates mainly on lower consumption. Tanner EDA was used to build and simulate this complete schematic. Materials having a lesser environmental effect are chosen, such as those that use fewer resources or are simpler to recycle after a product’s lifespan and sustainability.

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