Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor

Pon, Adhithan; Carmel, A. Santhia; Bhattacharyya, Arkaprava; Ramesh, R.

doi:10.1016/j.spmi.2017.11.043

Cited by 11 publications

(4 citation statements)

References 7 publications

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“…Remarkable growth in semiconductor industry has been attained by reducing the dimensions of metal oxide semiconductor (MOS) devices without affecting its electrical characteristics. Conventional MOS transistors endure large power dissipation as well as leakage current 1 . This ineffectiveness had been taken care by small size MOSFET, where SiO 2 layer has been grown as a gate dielectric on semiconductor substrate as it provides better electrical insulation 2 .…”

Section: Introductionmentioning

confidence: 99%

“…Conventional MOS transistors endure large power dissipation as well as leakage current. 1 This ineffectiveness had been taken care by small size MOSFET, where SiO 2 layer has been grown as a gate dielectric on semiconductor substrate as it provides better electrical insulation. 2 The reduction in device size minimizes the gate control on region, causes several problems like short channel effects (SCE's) and hot carrier effects (HCE's).…”

Section: Introductionmentioning

confidence: 99%

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SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

Neeraj

Goel

Sharma

et al. 2022

Int J Numerical Modelling

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In this paper, silicon carbide-based analytical model for gate-stack dual metal nanowire field effect transistor (gate-stack DM NW FET) has been analyzed by solving the 2D Poisson's equation using parabolic approximation method for electric potential, subthreshold current and subthreshold slope. The results have been examined for various silicon carbide film depth and channel length. The results predicted by the analytical model have excellent agreement with simulated results obtained by ATLAS 3D device simulator. A gate-stack having high k-dielectric material, that is, Hafnium oxide (HfO 2 ) along with aluminum oxide (Al 2 O 3 ) has been used. Also, performance characteristics of gate-stack DM NW FET have been compared with the performance characteristics of nanowire field effect transistor (NW FET), Nanowire field effect transistor (NW FET) (Sic) and dual metal nanowire field effect transistor (DM NW FET) (SiC). It is so proved that our proposed device, that is, gate-stack DM NW FET (4H-SiC) exhibits superior performance in terms of drain current (I ds) , transconductance (g m ), output conductance (g d ) and cut off frequency (f T ) than the existing devices.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

Neeraj

Goel

Sharma

et al. 2022

Int J Numerical Modelling

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“…In spite of these advantages, TFET devices meet considerable challenges in producing better ON-state current (ION). To overcome this problem, several typical device structures with gate and material engineering have been studied [7][8][9][10][11][12][13][14]. Moreover, the supply voltage (VDD) needs to be lowered with device downsizing for low power applications.…”

Section: Introductionmentioning

confidence: 99%

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Dutta¹,

Paitya²

2021

J. Nano- Electron. Phys.

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Influence of triple material having different work functions have been designed and investigated on a double gated P-i-N tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) for improved device performance. A III/V compound material (InAs) has been used in the source region for this n-channel heterojunction tunnel FET, because of which stress -strain effect results better tunneling. Graphene, being a low band gap material, has been used as nano ribbon to tune suitably the energy bandgap as less as possible. In this paper, the three different materials are introduced to restrict the drain -source reverse tunneling and also improve the TFET device performance in terms of surface potential distribution, lateral -vertical electric field variation and transfer characteristics. This triple material-based DG-PiN-TGNFET structure provides better subthreshold swing of 18.56 mV/decade at 0.5 V supply voltage compared to single and double material based double gated TGN-FET structures. The entire simulation has been performed using two-dimensional mathematical TCAD device software. Moreover, the low threshold voltage encourages the proposed device best suitable for low power logic applications.

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“…To improve these limitations, the drain current equation can be written as: Where m * is the effective mass, E g is the material bandgap, is range of energy over which the tunneling can occur, e is an electron charge, t ox and t si are oxide and silicon film thickness, ε ox and ε si are the dielectric constants. ħ is the plank's constant [4][5][6]. Equation (1) shows that the tunneling current in a TFET can be raised by introducing a low band gap material.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

Dutta¹,

Paitya²

2019

IJITEE

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In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2 , ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/µm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2 -SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

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Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor

Cited by 11 publications

References 7 publications

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

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