<scp>SiC</scp>‐based analytical model for gate‐stack dual metal nanowire<scp>FET</scp>with enhanced analog performance

Neeraj,; Goel, Anubha; Sharma, Shobha; Rewari, Sonam; Gupta, Radhey S.

doi:10.1002/jnm.2986

Cited by 7 publications

(15 citation statements)

References 28 publications

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“…V fbi = Φ m1 ÀΦ m2 with Φ m1 metal work function and Φ m2 silicon carbide/silicon work function. Capacitance per unit area of the oxide is represented as 23 :…”

Section: Analytical Modelmentioning

confidence: 99%

“…Feature length is represented by λ. 23 Furthermore, the following have been derived by calculating C 1 , C 2 , and λ. 23,24…”

Section: Analytical Modelmentioning

confidence: 99%

“…Capacitance per unit area of the oxide is represented as 23 :

C_{italicOx} = \frac{2 ε_{italicox}}{t_{italicSiC} \ln (1 + (\frac{2 t_{oxeff}}{t_{italicSiC}}))},

where

t_{italicoxeff} = t_{italicox} + \frac{ϵ_{ox}}{ϵ_{italichigh - k}} t_{high - k} .

…”

Section: Analytical Modelmentioning

confidence: 99%

“…(𝜌, z 1 , 𝑇) and (𝜌, z 2 , 𝑇) represents the central potential for gate region 1 and gate region 2, respectively, V gf 1 = V gs − V fb 1 and V gf 2 = V gs − V fb 2 , where V fb 1 = Φ m1 −Φ Si/4H‐SiC , V fb 2 = Φ m2 −Φ Si/4H‐SiC . Feature length is represented by λ 23 . Furthermore, the following have been derived by calculating C 1 , C 2 , and λ 23,24 …”

Section: Analytical Modelmentioning

confidence: 99%

“…Feature length is represented by λ 23 . Furthermore, the following have been derived by calculating C 1 , C 2 , and λ 23,24

ψ (0, z_{1}, T) = V_{gf 1} + V + H + \frac{V_{italicds} - V_{gf 1} - H \sinh (\frac{z_{1}}{λ}) - V_{gf 1} + H \sinh (\frac{L - z_{1}}{λ})}{\sinh (\frac{L}{λ})},

ψ (0, z_{2}, T) = V_{gf 2} + V + H + \frac{V_{italicds} - V_{gf 2} - H \sinh (\frac{z_{2}}{λ}) - V_{gf 2} + H \sinh (\frac{L - z_{2}}{λ})}{\sinh (\frac{L}{λ})} .

…”

Section: Analytical Modelmentioning

confidence: 99%

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Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Neeraj

Sharma

Goel³

et al. 2022

Int J Numerical Modelling

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This article presents an analytical study and effect of temperature (T = 100, 200, 300, 400 K) on various parameters of gate-stack dual metal nanowire field-effect transistor (gate-stack DM NW) FET (4H-SiC) and gate-stack dual metal nanowire field-effect transistor (gate-stack DM NW FET) (Si). The parabolic approximation is used to solve the 2D Poisson's equation for surface potential, electric field, drain current (I ds ), transconductance (g m ), output conductance (g d ), and analog performance is evaluated. Electron concentration, electron velocity, drain induced barrier lowering, DIBL, and noise figure (NF) have also been investigated for a fair comparison and shows that 4H-SiC based gate-stack DM NW FET device is more insensitive to temperature changes than the silicon-based gate-stack DM NW FET. Furthermore, gatestack DM NW FET (4H-SiC) has better electrical performance with temperature variation than gate-stack DM NW FET (Si). The simulations have been carried out using the ATLAS 3D device simulator. Analytical results are in close agreement with the simulated results.

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“…V fbi = Φ m1 ÀΦ m2 with Φ m1 metal work function and Φ m2 silicon carbide/silicon work function. Capacitance per unit area of the oxide is represented as 23 :…”

Section: Analytical Modelmentioning

confidence: 99%

“…Feature length is represented by λ. 23 Furthermore, the following have been derived by calculating C 1 , C 2 , and λ. 23,24…”

Section: Analytical Modelmentioning

confidence: 99%

“…Capacitance per unit area of the oxide is represented as 23 :