Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

Moaiyeri, Mohammad Hossein; Razi, Farzad

doi:10.1007/s10825-017-0980-0

Cited by 57 publications

(32 citation statements)

References 23 publications

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“…The band gap of carbon nanotube is dominantly dependent on the CNT diameter that governs various electrical and physical properties of the CNT and hence CNTFET. The band gap (E g ) of CNT can be calculated as [18,19]:…”

Section: Carbon Nanotube As a Device Channelmentioning

confidence: 99%

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DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Singh

Prasad

Kumar

2020

Mater. Res. Express

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The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET-reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc Unfortunately at 22 nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (E g ) are extracted by using MedeA tool's VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco's Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (I D -V GS ) and output (I D -V DS ) characteristics have been intensively studied and parameters including I ON /I OFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (V TH ) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and I ON/ I OFF ratio 7.17e+06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.

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Section: Carbon Nanotube As a Device Channelmentioning

confidence: 99%

“…Also, some other parameters such as effective mobility (), inversion capacitance (), subthreshold coefficient (), strong inversion threshold voltage (), carrier velocity (), source resistance () and drain resistance are dependent to CNT diameter. In CNTFET device threshold voltage can be determined as [18,21]:…”

Section: Carbon Nanotube As a Device Channelmentioning

confidence: 99%

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Singh

Prasad

Kumar

2020

Mater. Res. Express

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“…ey are a typical representative of sub-10-nm gate-all-around (GAA) transistors. ere are several types of CNTFETs: MOSFET-like CNTFETs, Schottkybarrier CNTFETs, and tunneling CNTFETs [35]. Compared to conventional CMOS technology, the CNTFETs show better device performance-sub-10-nm CNT transistors outperform MOS transistors with more than 4× the current density [36].…”

Section: D Integrationmentioning

confidence: 99%

Technology and Modeling of Nonclassical Transistor Devices

Angelov

Nikolov

Hristov

2019

Journal of Electrical and Computer Engineering

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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“…Average power variation of proposed and existing designs with respect to variation in diameter of CNT chirality reduces the width of transistors as shown by equation(4). In addition, the proposed circuit has lower transistor count compared to other techniques.The FOM is a performance metrics, which determines the effectiveness and efficiency of the circuit.…”

mentioning

confidence: 94%

“…[1][2][3] The power dissipation in a domino circuit is the sum of leakage power consumption due to leakage current in OFF transistors, switching power due to charging and discharging of circuit capacitances, and short circuit power due to short between the power supply and ground. 4 In order to reduce the power consumption of domino circuits, both static and dynamic power dissipation must be taken into consideration. Because of nonstop scaling, CMOS logic experiences different difficulties like reduced control on gate terminal, SCEs (short channel effects) and high power consumption due to leakage current.…”

Section: Introductionmentioning

confidence: 99%

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adderdesigned using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder. K E Y W O R D SCNFET, Domino, Dynamic, FOM, VLSI

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Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

Cited by 57 publications

References 23 publications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Technology and Modeling of Nonclassical Transistor Devices

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

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