PCA-1: a fully asynchronous, self-reconfigurable LSI

Konishi, Ryusuke; Ito, H.; Nagoya, Akira; Oguri, Kazuta; Imlig, Norbert; Shiozawa, Tsunemichi; Inamori, Minoru; Nagami, Kouichi

doi:10.1109/async.2001.914069

Cited by 31 publications

(13 citation statements)

References 6 publications

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“…At room temperature and with a supply voltage of 1.8 V, we measured a throughput of 674 MHz. To our knowledge, the only other published configurable asynchronous circuit that was fabricated was the PCA-1 architecture, and they reported a peak throughput of 20 MHz in a 0.35μm CMOS process [2]. Even adjusting for feature size, our results are better by over an order of magnitude.…”

Section: Introductionsupporting

confidence: 66%

A High-Performance Asynchronous FPGA: Test Results

Fang

Teifel

Manohar

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)

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Section: Introductionsupporting

confidence: 66%

A High-Performance Asynchronous FPGA: Test Results

Fang

Teifel

Manohar

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)

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“…At room temperature with a supply voltage of 1.8 V (nominal), we measured a throughput of 674 MHz. To our knowledge, the only other published configurable asynchronous circuit that was fabricated is the PCA-1 architecture, and they reported a peak throughput of 20 MHz in a 0.35µm CMOS process [8].…”

Section: Resultsmentioning

confidence: 99%

“…Other architectures were based on "porting" a clocked FPGA architecture, and the result was relatively low throughput [6], [15], [8]. More recently, there has been work that is similar in spirit to the design described here, where an asynchronous FPGA architecture based on programmable pipeline stages was proposed [24].…”

Section: Introductionmentioning

confidence: 95%

Reconfigurable Asynchronous Logic

Manohar

2006

IEEE Custom Integrated Circuits Conference 2006

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Abstract-Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuitlevel flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.

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“…Two distinct types of cells, that are always paired, are used: a timing cell that implements the control-path using asynchronous signaling and a data cell that uses same structures as a synchronous FPGA. A similar approach was also suggested in [115]; however, that design opted for a more elaborate control path unit.…”

Section: Asynchronous Architecturesmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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PCA-1: a fully asynchronous, self-reconfigurable LSI

Cited by 31 publications

References 6 publications

A High-Performance Asynchronous FPGA: Test Results

A High-Performance Asynchronous FPGA: Test Results

Reconfigurable Asynchronous Logic

FPGA Architecture: Survey and Challenges

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