2017
DOI: 10.1117/12.2260155
|View full text |Cite
|
Sign up to set email alerts
|

Patterning control strategies for minimum edge placement error in logic devices

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
19
0

Year Published

2019
2019
2024
2024

Publication Types

Select...
7
1

Relationship

0
8

Authors

Journals

citations
Cited by 33 publications
(21 citation statements)
references
References 1 publication
0
19
0
Order By: Relevance
“…The accuracy of alignment for nanoscale features is a prime bottleneck that is currently limiting the advancement to smaller technology nodes in the semiconductor industry. Misalignment issues arise from the many lithography steps that are employed for the fabrication of device stacks. Therefore, area-selective atomic layer deposition (ALD) is gaining interest for its potential role in self-aligned fabrication schemes . ALD is a cyclic deposition technique that relies on sequential, self-limiting surface reactions of two or more reactants (i.e., precursors) .…”
Section: Introductionmentioning
confidence: 99%
“…The accuracy of alignment for nanoscale features is a prime bottleneck that is currently limiting the advancement to smaller technology nodes in the semiconductor industry. Misalignment issues arise from the many lithography steps that are employed for the fabrication of device stacks. Therefore, area-selective atomic layer deposition (ALD) is gaining interest for its potential role in self-aligned fabrication schemes . ALD is a cyclic deposition technique that relies on sequential, self-limiting surface reactions of two or more reactants (i.e., precursors) .…”
Section: Introductionmentioning
confidence: 99%
“…[25][26][27] No matter what it is called the combined effect of CD and overlay error is well known to the design community as a key variable that not only affects space between two features but also design constructs that require overlap and intersect area (IA) between two shapes. 28 Edge placement error [29][30][31][32] and relative edge placement error 33 are also terms that describe the effect of CD and overlay error together.…”
Section: Summary and Future Workmentioning
confidence: 99%
“…Ultraviolet (UV) photolithography technology is one of the key components in the semiconductor industry. Advancement in the transistor density of integrated circuits (ICs) can be partially attributed to the improvement in the UV photolithography process. , When scaling down the size of a metal oxide semiconductor field effect transistor (MOSFET), mask misalignment became one of the major limitations of UV photolithography. To solve the issue of mask misalignment, Bencher et al proposed the self-aligned chemical vapor deposition (CVD) [or area-selective CVD (AS-CVD)] spacer double-patterning method which has evolved to a self-aligned quadruple-patterning method in recent years. , The spacer or etch stop material when selectively deposited onto the preferred locations of a pre-etched structure allows the pitch of the IC to be reduced by half. Since then, AS-CVD has garnered attention as an alternative patterning method.…”
Section: Introductionmentioning
confidence: 99%