Pathfinding of Ru-Liner/Cu-Reflow Interconnect Reliability Solution

Wu, Zhi-Yuan; Chen, Feng; Shen, Gang; Hu, Yufei; Pethe, Shirish A.; Lee, Joung Joo; Tseng, Jennifer F.; Suen, Wesley; Vinnakota, Ramkumar; Kashefizadeh, Keyvan; Naik, Mehul

doi:10.1109/iitc.2018.8430464

Cited by 3 publications

(5 citation statements)

References 4 publications

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“…Co caps have been established as a standard process since the emergence of 14 nm technology. As a result, a significant improvement in EM performance has been observed with a Ru liner as the Co cap thickness increases [57]. It has also been demonstrated that the EM problem arises from the diffusion of Co from the cap to the liner due to the Co concentration gradient between the two [57][58][59].…”

Section: Tan Barrier/liner Scalingmentioning

confidence: 97%

“…However, the resistance of Ru was about 10% higher than that of Co as revealed by the temperature coefficient of resistance (TCR), which was believed to be due to interface and GB scattering. A Co liner has also been shown to outperform a Ru liner in terms of EM characteristics [57].…”

Section: Tan Barrier/liner Scalingmentioning

confidence: 99%

“…As a result, a significant improvement in EM performance has been observed with a Ru liner as the Co cap thickness increases [57]. It has also been demonstrated that the EM problem arises from the diffusion of Co from the cap to the liner due to the Co concentration gradient between the two [57][58][59]. Thus, a Co-doped Ru liner has been proposed to overcome this problem, and EM improvements have been reported [58,59].…”

Section: Tan Barrier/liner Scalingmentioning

confidence: 99%

“…Similarly, at the interface, there is an adhesion issue between the liner and Cu. Therefore, EM improvement must be verified when evaluating new materials such as Co and Ru liners and reducing barrier/liner thickness [46,47,[57][58][59]75]. For the GBs, the lower the metal width, the more difficult it is to improve the EM because the grain growth is limited by the metal width.…”

Section: Electromigrationmentioning

confidence: 99%

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Recent Trends in Copper Metallization

Kim

2022

Electronics

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The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO2 interconnects, but now that the technology generation has reached 1× nm or lower, a number of limitations have become apparent. Due to the integration limit of low-k materials, the increase in the RC delay due to scaling can only be suppressed through metallization. As a result, various metallization methods have been proposed, including traditional barrier/liner thickness scaling, and new materials and integration schemes have been developed. This paper introduces these methods and summarizes the recent trends in metallization. It also includes a brief introduction to the Cu damascene process, an explanation of why the low-k approach faces limitations, and a discussion of the measures of reliability (electromigration and time-dependent dielectric breakdown) that are essential for all validation schemes.

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Section: Tan Barrier/liner Scalingmentioning

confidence: 97%

Section: Tan Barrier/liner Scalingmentioning

confidence: 99%

Section: Tan Barrier/liner Scalingmentioning

confidence: 99%

Section: Electromigrationmentioning

confidence: 99%

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Recent Trends in Copper Metallization

Kim

2022

Electronics

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“…Ruthenium (Ru) and cobalt (Co) are candidate materials to replace the Cu filling in interconnects and vias, in diffusion barriers and in liners for adhesion [8,11]. In 2018, Intel adopted Co to substitute Cu lines in local interconnects on 10 nm technology.…”

Section: Introductionmentioning

confidence: 99%

Effect of Lines and Vias Density on the BEOL Temperature Distribution

Nunes

Orio²

2019

JICS

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A method to calculate the temperature distribution on the BEOL structure and its impact on the EM in a design environment has been developed and implemented. The study for a 45 nm technology indicated a large temperature variation from the local to the global interconnects, which should be considered for the EM induced resistance increase of the line, in contrast to the standard analysis through a fixed operation temperature throughout the BEOL. The results show that a significant additional temperature above 50°C exist on the layers M1 to M6 due the power dissipated from transistors. The temperature reduction on the local layer is evaluated increasing the number of vias and enlarging the interconnect lines, both with a direct influence on the BEOL thermal distribution. A reduction of 62.9°C is obtained for M1 layer, considering a fraction volume of 40% for lines and 6% for vias.

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