Effect of Lines and Vias Density on the BEOL Temperature Distribution

Nunes, R. O.; Orio, R. L. de

doi:10.29292/jics.v14i2.63

Cited by 3 publications

(1 citation statement)

References 28 publications

(47 reference statements)

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“…where Ö and Ñ are related to 𝑘 𝑚 , 𝑘 𝑖 , the length and the thickness of the lines [133]. The dimensionless parameters Ö and Ñ can be approximated to 1, however, for interconnect lines with dimensions above 10 Ûm [137]. The model above allows estimating the temperature increase in interconnects as a function of the power dissipated by the circuit.…”

Section: Self-heating From Transistorsmentioning

confidence: 99%

Study of electromigration in integrated circuits at design level

Nunes¹

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Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, because it causes reliability problems. Operation at high temperatures and current densities accelerates the damage, increasing the interconnect resistance and, therefore, reducing the circuit lifetime. This issue has been accentuated with the technology downscaling. To guarantee the interconnect reliability and, as a consequence, the integrated circuit reliability, traditional methods based on the so-called Blech Effect and on the maximum allowed current density are implemented during interconnect design. These methods, however, do not take into account the impact of the electromigration on the circuit performance.In this work the traditional approach is extended and a method to evaluate the effect of the electromigration in an integrated circuit performance is developed. The method is implemented in a tool which identiĄes the critical interconnect lines of an integrated circuit and suggests the proper interconnect width based on different criteria to mitigate the electromigration damage and to increase the reliability. In addition, the variation of performance parameters of the circuit as an interconnect resistance changes is determined.The tool is incorporated into the design Ćow of the integrated circuit and uses the data from design kits and reports directly available from the design environment.An accurate analysis of the temperature distribution on the interconnect structure is essential to a better assessment of the interconnect reliability. Therefore, a model to compute the temperature on each metallization level of the interconnect structure is implemented.The temperature distribution on the metallization layers of different technologies is investigated. It is shown that the temperature in the Metal 1 of the Intel 10 nm can increase by 75 K, 12 K higher than in the Metal 2. As expected, the layers that are closer to the transistors undergo a more signiĄcant temperature increase.The tool is applied to evaluate the interconnects and the robustness of different circuits, namely a ring oscillator, a bandgap voltage reference circuit, and an operational ampliĄer, against electromigration. The operational ampliĄer, in particular, is thoroughly studied.The proposed methodology identiĄes critical interconnects which under electromigration cause large variations in the performance of the circuit. In a worst-case scenario, the cutoff frequency of the circuit varies by 65% in 5 years of operation. An interesting Ąnding is that the proposed methodology identiĄes critical interconnects which would not be identiĄed by the traditional criteria. These interconnects have current densities below the limit recommended by the design rules. Nevertheless, one of such an interconnect leads to a variation of 30% in the gain of the operational ampliĄer. In summary, the proposed tool veriĄed that from the 20% paths with a critical current density, only 3% degrades signiĄcantly the circuit performance.This work brings the study of the reli...

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Section: Self-heating From Transistorsmentioning

confidence: 99%

Study of electromigration in integrated circuits at design level

Nunes¹

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Numerical Model for Understanding Interconnection Thermal Reliability Mechanism of Cu Via in Back End of Line (BEOL)

Wang

Sun

Fang

et al. 2021

2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)

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Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

Nunes

Bohorquez²,

Orio³

2020

JICS

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This paper demonstrates a finite element model to investigate the temperature change of the interconnects of an integrated circuit due to the power dissipation of the transistors in the substrate. The temperature of the local interconnect is more significantly affected, exhibiting an increase of 49 K and 34 K, for the Metal 1 and Metal 2, respectively. We discuss the impact of the temperature increase in the electromigration and, as a consequence in the lifetime of an operational amplifier, which demonstrates the importance of considering the metallization temperature distribution in the design stage.

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Effect of Lines and Vias Density on the BEOL Temperature Distribution

Cited by 3 publications

References 28 publications

Study of electromigration in integrated circuits at design level

Study of electromigration in integrated circuits at design level

Numerical Model for Understanding Interconnection Thermal Reliability Mechanism of Cu Via in Back End of Line (BEOL)

Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

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