Path selection for monitoring unexpected systematic timing effects

Callegari,; Bastani,; Wang, Li-C.; Chakravarty,; Tetelbaum,

doi:10.1109/aspdac.2009.4796575

Cited by 14 publications

(9 citation statements)

References 11 publications

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“…However, the problem of representative path selection is outside the scope of this paper and is studied separately, such as in [3]. While our framework can take as input any method for selecting and measuring representative paths, the important factor in our simulations is to ensure that the measured paths are indeed representative so they can more effectively reflect the silicon impact.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…For a fabricated chip, the degree of variation might be such that the delays of some of the paths exceed their timing requirements. We assume such paths are isolated and their delays are measured as discussed in [1], [3], [5], [7], [9]. Moreover, we assume the delays of additional speedpaths are also measured.…”

Section: Preliminariesmentioning

confidence: 99%

“…Note that our focus is on the segment identification problem, assuming the failing speedpaths are provided. We assume isolation of failing speedpaths is done using existing works such as [1], [3], [5], [7], while post-silicon path delay measurement is done using existing techniques such as [9].…”

Section: Problem Definitionmentioning

confidence: 99%

“…In [1], a statistical learning approach is proposed to predict the failing speedpaths by measuring the delays of a small set of representative paths at the post-silicon stage. To help identify such representative paths, in [3], a technique is proposed which relies on defining a set of basic features (e.g., the number or types of logic gates) to rank the target speedpaths. In [5], a manuallyguided technique is used to isolate failing speedpaths, via combination of techniques including clock shrinkage and using a debug tester.…”

Section: Introductionmentioning

confidence: 99%

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Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Xie

Davoodi

Saluja

2010

Proceedings of the 47th Design Automation Conference

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We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay larger than their estimated delays at the pre-silicon stage. We refer to such segments as "failing segments" and we rank them according to their degree of failure. Diagnosis of failing segments alleviates the problem of lack of observability inside a path. Moreover, root-cause analysis, and post-silicon tuning or repair, can be done more effectively by focusing on the failing segments. We propose an Integer Linear Programming formulation to breakdown a path into a set of nonfailing segments, leaving the remaining to be likely-failing ones. Our algorithm yields a very high "diagnosis resolution" in identifying failing segments, and in ranking them.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Preliminariesmentioning

confidence: 99%

Section: Problem Definitionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Xie

Davoodi

Saluja

2010

Proceedings of the 47th Design Automation Conference

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“…For example, an adaptive substrate-bias control for each manufactured chip has been proposed to compensate for delay change resulting from threshold voltage variations [3]. In LSI testing, the idea of adaptive testing, in which a set of test paths is altered to apply the most suitable one for a chip, has been proposed [4]- [6]. Both of these techniques rely on the device-parameter estimations, such as threshold voltages of transistors, of an individual chip.…”

Section: Introductionmentioning

confidence: 99%

Device-Parameter Estimation through IDDQ Signatures

Shintani

Satō

2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a novel technique for the estimation of deviceparameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.

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On-die parameter extraction from path-delay measurements

Takahashi

Uezono

Shintani³

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

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Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed technique, delays of a set of paths consisting of different logic cells are monitored. Based on the pre-characterized parameter to delay sensitivity, the process variation of a chip is estimated as an inverse problem. Discussion of desirable logic cell combination to form paths that maximize estimation accuracy is presented. Measurement of ring oscillator arrays composed of standard and customized logic cells resulted in consistent estimation of threshold voltages. Measurement accuracy is greatly enhanced by the proposed good logic cell combinations.

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Path selection for monitoring unexpected systematic timing effects

Cited by 14 publications

References 11 publications

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Device-Parameter Estimation through IDDQ Signatures

On-die parameter extraction from path-delay measurements

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