Path resizing based on incremental technique

Cremoux, Séverine; Azémard, Nadine; Auvergne, D.

doi:10.1109/iscas.1998.705219

Cited by 9 publications

(3 citation statements)

References 11 publications

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“…This tool allows to consider an user specified limited number of paths [11][12], for easy application and validation of the different path optimization criteria. The delay model implemented in this tool is based on an analytical representation of the timing performance, allowing to obtain for any logic gate, in its environment, an accurate evaluation of its switching delay and output transition time.…”

Section: Optimization Toolmentioning

confidence: 99%

Performance Metric Based Optimization Protocol

Michel

Verle

Maurine

et al. 2004

Lecture Notes in Computer Science

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Optimizing digital designs implies a selection of circuit implementation based on different cost criteria. Post-processing methods such as transistor sizing, buffer insertion or logic transformation can be used for optimizing critical paths to satisfy timing constraints. However most optimization tools are not able to select between the different optimization alternatives and have high CPU execution time.In this paper, we propose an optimization protocol based on metrics allowing to characterize a path and to select the best optimization alternative. We define a way to characterize the design space of any circuit implementation. Then we propose a constraint distribution method allowing constraint satisfaction at nearly minimum area. This quasi optimal tool is implemented in an optimization tool (POPS) and validated by comparing the area necessary to satisfy delay constraints applied to various benchmarks (ISCAS'85) to that resulting from an industrial tool.

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Section: Optimization Toolmentioning

confidence: 99%

Performance Metric Based Optimization Protocol

Michel

Verle

Maurine

et al. 2004

Lecture Notes in Computer Science

Self Cite

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show abstract

“…This tool allows to consider an user specified limited number of paths [11][12], for easy application and validation of the different path optimization criteria. The delay model implemented in this tool is based on a design oriented closed-form representation of the timing performance, allowing to obtain for any logic gate, in its environment, an accurate evaluation of its switching delay and output transition time.…”

Section: Optimization Toolmentioning

confidence: 99%

Low Power Oriented CMOS Circuit Optimization Protocol

Verle

Michel

Azémard

et al.

Design, Automation and Test in Europe

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“…The implemented incremental technique allows to obtain as well the enumeration in a non increasing order of delays of the longest paths [14] than the classification in an increasing order of delays of the shortest paths. We limit here our presentation to the shortest path search.…”

Section: Incremental Search Path Algorithmmentioning

confidence: 99%

Delay-power performance analysis

Cremoux

Aline

Azémard

et al.

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)

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Based on an incremental path search algorithm, this paper addresses the problem of low power performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Demonstration of this technique is given on examples of path enumeration and optimization evaluated on several ISCAS '85 benchmarks. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from EPIC tool and SPICE used as a reference.

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Path resizing based on incremental technique

Cited by 9 publications

References 11 publications

Performance Metric Based Optimization Protocol

Performance Metric Based Optimization Protocol

Low Power Oriented CMOS Circuit Optimization Protocol

Delay-power performance analysis

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