Low Power Oriented CMOS Circuit Optimization Protocol

Verle, Alexandre; Michel, Xavier; Azémard, Nadine; Maurine, Philippe; Auvergne, D.

doi:10.1109/date.2005.202

Cited by 2 publications

(5 citation statements)

References 16 publications

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“…For the lower bound, we apply the method of equal sensitivity previously developed for combinatorial paths [1]. So, for a path, the inferior delay bound is easily obtained by canceling the derivatives of the path delay with respect to the input capacitance of its gates.…”

Section: Critical Path Problem Illustrationmentioning

confidence: 99%

“…For a simplified delay model [10], based on the transition time of a gate, the local minimum of an array of two gates (Fig. 2) is obtained by sizing the input capacitance of each gate, following: (1) where Sk represents the current possibilities of the gate K, C L the load of this gate and C REF a reference capacitance value, defined from the minimum value available in the process.…”

Section: Local Minimum Definitionmentioning

confidence: 99%

“…− Initially, on the critical path, each gate is sized at a reference value, C REF , equal to the minimum size allowed by the process or the library. − To reduce the CPU time, to obtain a fast evaluation of the path delays and to propose a simple heuristic, we use a first order delay model [10], based on the gate transition time, as…”

Section: Fig 6 Circuit With a Critical Path And Its Divergence Branchmentioning

confidence: 99%

“…The goal is to size the gates of Branch2 to obtain the value of the input capacitance of the divergence branch (C IN1,2 ), and then the value of the γ coefficient. Consequently, we cannot apply the constant sensitivity method, because with this method the input capacitance of the branch is fixed [1] in order to have a convex delay function. So, to obtain an approximate but fast sizing, we use the heuristic approach of [11].…”

Section: Fig 6 Circuit With a Critical Path And Its Divergence Branchmentioning

confidence: 99%

“…To effectively reduce the number of loops, we extend, in this paper, the equal sensitivity method defined on a path [1] to the sizing of all the circuit paths. To solve the path sizing problem two particular structures must be considered, the divergence and re-convergence branches.…”

Section: Introductionmentioning

confidence: 99%

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Speed Indicators for Circuit Optimization

Verle

Landrault

Maurine

et al. 2005

Lecture Notes in Computer Science

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Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process.

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Section: Critical Path Problem Illustrationmentioning

confidence: 99%

Section: Local Minimum Definitionmentioning

confidence: 99%

Section: Fig 6 Circuit With a Critical Path And Its Divergence Branchmentioning

confidence: 99%

Section: Fig 6 Circuit With a Critical Path And Its Divergence Branchmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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