Delay-power performance analysis

Abstract

Based on an incremental path search algorithm, this paper addresses the problem of low power performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Demonstration of this technique is given on examples of path enumeration and optimization evaluated on several ISCAS '85 benchmarks. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from EPIC tool and SPICE used as a reference.