Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation

Hess, C.; Stine, B.E.; Weiland, L.H.; Mitchell, T.; Karnett, M.; Gardner, K.

doi:10.1109/icmts.2002.1193190

Cited by 6 publications

(5 citation statements)

References 5 publications

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“…Manufacturing limitations create risks when vias are introduced while changing layers. Long recognized as one of the yield-limiting features [17], this forms one component of the interconnect cost. A general equation to represent the via cost is:…”

Section: ) Layer Change Costmentioning

confidence: 99%

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

Subramaniyan

Larsson-Edefors

2014

2014 5th European Workshop on CMOS Variability (VARI)

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Complex system implementations combined with the latest technology nodes allow us to implement hardware for versatile applications. The ever increasing demand for quick time-to-market has led to the widespread use of Intellectual Property (IP) in ASIC design methodologies. These developments, in addition to manufacturing limitations, make early prediction of manufacturability for complete systems challenging. We present MIDAS: a scalable, IP-inclusive model to predict system manufacturability. Results from applying MIDAS to an embedded processor system reveals that several useful insights can be gained towards realizing yield budgets for complex systems allowing quicker co-optimization of all implementation goals.

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Section: ) Layer Change Costmentioning

confidence: 99%

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

Subramaniyan

Larsson-Edefors

2014

2014 5th European Workshop on CMOS Variability (VARI)

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“…Some of the most significant systematic effects that cause functional yield loss include: via/via stack failure as a function of interconnect length, poly-metal bridging, metal shorts/opens as a function of width vs. spacing, misalignment and line-end shortening. Characterization of such effects in silicon requires specialized structures and a proper Design Of Experiments around the layout variables, as for example it is shown in [3].…”

Section: Design Systematic Yield Loss Mechanismsmentioning

confidence: 99%

An effective DFM strategy requires accurate process and IP pre-characterization

Guardiani

Bertoietti

Dragone

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…The absolute accuracy of predicted vs. actual yield is excellent (rt2%) in all cases except for product E (-9%), which indicates an existing yield loss mechanism not captured by the characterization structures in Tab. 1 and hence not accurately modeled by (5). The metric derived in (8) is more relevant than absolute percent yield improvement as it directly applies to cost benefit trade-offs when used with manufacturing volume projections.…”

Section: -1 -3mentioning

confidence: 98%

“…1 must take into account the overall throughput capability as a function of testing and analysis. Novel structures that optimize the statistical sample size per test structure are available and reduce the test time and silicon area required for accurate characterization [5]. Nonetheless, the amount of data generated by a comprehensive test structure set remains massive.…”

Section: Test and Analysis Infrastructurementioning

confidence: 99%

Proactive design for manufacturing (DFM) for nanometer SoC designs

Guardiani

Dragone

McNamara

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

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In this paper, we will propose an innovative DFM (Design for Manufacturability) design flow. This flow achieves designs for logic products that are much more manufacturable than those using traditional design flows in nanometer technologies. The proposed DFM design flow is unique because it integrates manufacturability informationextracted directly from the target nanometer process-into the timing-driven synthesis and P&R cost function. As such, the designer is able to easily analyze optimal die size, yield, and performance trade-offs and seamlessly account for them before releasing the design to reticle creation. This proposed design flow system is comprised of three major elements:A DFM extension library, which creates "Yield Strength" variants of the basic logic functions in the library. 0A new design view data-file containing a precharacterized set of design attributes extracted from the cell library layouts and the required target process parameters extractions. A set of sofhare elements that plug the manufacturability information into the standard IC design creation and analysis flow.The EDA tools interact with these elements to determine the most manufacturable mapping and arrangement of any given logic function onto the physical library. The application of the proposed design flow in various 130nm designs will be presented. These will demonstrate the validity of the proposed approach, where DFM trade-offs are made early in a design effort, and will illustrate the practical advantages and implications of this approach in a nanometer design flow.

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Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation

Cited by 6 publications

References 5 publications

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

An effective DFM strategy requires accurate process and IP pre-characterization

Proactive design for manufacturing (DFM) for nanometer SoC designs

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