Passivation of Textured Silicon Wafers:Influence of Pyramid Size Distribution, a-Si:H Deposition Temperature, and Post-treatment

Evolution of the Charge Carrier Lifetime Characteristics in Crystalline Silicon Wafers During Processing of Heterojunction Solar Cells

“…It was found, that increasing the temperature up to 190° C leads to an increase of the charge carrier lifetime to a maximum value of 3.3 ms, which is promoted by the passivation of the (i)a-Si:H/c-Si interface by the highly mobile hydrogen. At 190° C a trade-off between hydrogen concentration and mobility is reached, as has been confirmed by optical measurements that at lower substrate temperatures the (i)a-Si:H layer contains larger amounts of hydrogen [9]. However, at lower temperatures diffusion is limited and accordingly interface passivation is suppressed, which results in lower charge carrier lifetimes.…”

“…The thickness of the (i)a-Si:H front layer was varied between 3 and 12 nm in order to optimize cell performance while the thicknesses of the rear side (i)a-Si:H and of the doped a-Si:H layers were kept constant. After deposition, the a-Si:H/c-Si stacks were either annealed at 200 C for 5 min or treated in a hydrogen plasma [8,9] depending on the experiment. For the solar cell preparation TCO layers (indium-tin-oxide (ITO), thickness 80 nm) were prepared by DC magnetron sputter deposition on the front and rear side of the previously deposited a-Si:H layers without additional sample heating and by addition of < 1.0 % oxygen to the Ar sputter gas [10].…”

“…It is known, that at rather low substrate temperatures up to 200 °C an improvement of τ eff can be expected [9]. This effect is due to the initially (i.e., after (i)a-Si:H deposition) rather high defect concentrations at the (i)a-Si:H/c-Si interface as well as in the (i)a-Si:H layer which can be efficiently saturated by the mobile hydrogen upon thermal annealing.…”

“…While the samples investigated in the previous section were coated on both surfaces with identical (i)a-Si:H layers at an at this stage not yet optimized deposition temperature of 170 °C, the focus in this section is on the optimization of (i)a-Si:H layer deposition parameters with respect to large carrier lifetimes. In this study a nominal (i)a-Si:H layer thickness of 17 nm was chosen, corresponding to an effective layer thickness of about 10 nm on textured substrates, as estimated from the effective surface enlargement by a factor of 1.73 [9]. Furthermore, samples with lower fractions of small pyramids (cf.…”

Dielectric surface passivation for silicon solar cells: A review

“…In the more common {111} texture Si surface, they found that a‐Si films still performed well. Stegemann et al showed that the pyramid size influenced the passivation quality of a‐Si films, yet Muñoz et al and Angermann et al showed that optimal texturing leads to a negligible loss in surface passivation, and Descoeudres et al reported the best performing a‐Si passivation in textured silicon with S eff = 7.6 and 14.4 cm s −1 in n‐ and p‐type, 4 Ωcm. One limiting factor in the application of a‐Si to solar cells is optical parasitic absorption.…”