Evolution of the Charge Carrier Lifetime Characteristics in Crystalline Silicon Wafers During Processing of Heterojunction Solar Cells

Spectral dependence of carrier lifetimes in silicon for photovoltaic applications

“…However, considering the minimum value of τ b =1 ms, we can estimate a lower bound S pass ≥ 5.7 cm/s from the model fit to the data. This lower bound value for bulk lifetimes and the estimated passivated surface recombination velocity range are consistent with other reports 39–41 for n-type HIT silicon.…”

High‐performance a‐Si1–xOx:H/c‐Si heterojunction solar cells realized by the a‐Si:H/a‐Si1–xOx:H stack buffer layer

“…We also observed a low FF when the thickness of the a‐Si 1– x O x :H buffer layer was above 5.0 nm. Conversely, a‐Si:H buffer layers with similar thicknesses are generally used in high‐efficiency a‐Si:H/c‐Si heterojunction solar cells . In this work, we will demonstrate that high V OC and high FF can also be achieved simultaneously by using a stack buffer layer of a‐Si:H/a‐Si 1– x O x :H in the a‐Si 1– x O x :H/c‐Si heterojunction solar cell, where µc‐Si 1– x O x :H was used as its emitter layer.…”

“…Photovoltaics has become one of the most important renewable‐energy technologies in recent years. Combining low‐cost thin‐film technology with crystalline silicon (c‐Si) solar cells, silicon heterojunction (SHJ) solar cells have recently received great attention . A high open‐circuit voltage ( V OC ) can be realized in SHJ solar cells as well as an improved high‐temperature performance .…”

“…Combining low‐cost thin‐film technology with crystalline silicon (c‐Si) solar cells, silicon heterojunction (SHJ) solar cells have recently received great attention . A high open‐circuit voltage ( V OC ) can be realized in SHJ solar cells as well as an improved high‐temperature performance . An intrinsic amorphous silicon (a‐Si:H) was introduced as a buffer layer between a doped layer and a c‐Si wafer so that excellent passivation could be realized on wafer surfaces .…”

Reduction of the interface defect density on crystalline silicon solar cell substrates by wet-chemical preparation of ultrathin SiOx passivation layers

“…In the next step, random pyramid textured substrate surfaces were prepared in KOH solution at temperatures of 80 °C using the isopropanol(IPA)-free and, thus, environmentally, safety and health compliant additive Alkatex Zero TM (GP Solar GmbH) [1]. According to previous investigations, optimized values of the depth of saw damage etch (SDE) and of the duration of texture etching were selected to obtain large minority charge carrier lifetimes, low reflection losses, and low recombination losses [1,6]. For the sake of comparison polished Si wafers were prepared and included in the next steps of preparation (denotes as reference samples).…”