Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Shimizu, Kazumi; Ishikawa, Tomoki; Togawa, Nozomu; Ikenaga, Takeshi; Goto, Satoshi

doi:10.1109/iccd.2005.83

Cited by 32 publications

(39 citation statements)

References 10 publications

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“…The results of [75], [48] and [76] all sit above the trend line, despite employing a large number of bits per LLR, as well as a moderate PCM size. This may be partially attributed to their implementation of quasi-cyclic LDPC codes, using partially-parallel architectures, leading to a very efficient use of hardware resources.…”

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 79%

“…In addition, this design also uses a sophisticated nonuniform quantisation scheme for the representation of LLRs, it employs a moderate number of bits per LLR and iterations, as well as implementing the full SPA. By contrast, the designs of [76] and [48] operate further away from capacity than may be expected, which is due to their use of the MSA.…”

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 79%

“…Many authors (e.g. [42], [47], [48]) mention the number of bits used in their FPGA-based LDPC decoders, but do not detail the quantisation scheme employed. Since non-uniform schemes require significantly more details than uniform representations, these cases are assumed to employ uniform quantisation and are marked with an asterisk in Table II. The maximum achievable clock frequency of an FPGAbased LDPC decoder depends largely on the capabilities of the FPGA employed, but also on some design decisions such as the critical path length.…”

Section: A Parametersmentioning

confidence: 99%

See 2 more Smart Citations

A Survey of FPGA-Based LDPC Decoders

Hailes

Maunder

et al. 2016

IEEE Commun. Surv. Tutorials

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Abstract-Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their insystem programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, processing latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoders.

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Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 79%

Section: B Relationships Between Parameters and Each Characteristicmentioning

confidence: 79%

Section: A Parametersmentioning

confidence: 99%

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A Survey of FPGA-Based LDPC Decoders

Hailes

Maunder

et al. 2016

IEEE Commun. Surv. Tutorials

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“…The component LDPC decoders computes the a posteriori probability as described in Shimizu, Ishikawa, Togawa, Ikenaga, and Goto (2005) using the sum-product algorithm with modifications to accommodate the a priori information.…”

Section: Pcgcm Decodermentioning

confidence: 99%

Parallel concatenated Gallager codes matrix and the effect of interleaver

Belgheit

Boukelif

Lakhder

et al. 2012

International Journal of Electronics

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We present a new class of concatenated codes which we call parallel concatenated Gallager codes matrix (PCGCM) using low-density parity-check component codes and a matrix organisation bits. We report simulation results for PCGCM that outperform those for comparable PCGC codes in additive white Gaussian noise channels. The effect of block and convolutional interleaving in a concatenated code called PCGCM is investigated in this article.

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“…Fully parallel architecture directly maps standard belief propagation (BP) algorithm into hardware by specifying connections between check nodes and variable nodes, which is the fastest but the routing congestion it induced is not tolerable [18]. Partially parallel decoder architecture achieves a good tradeoff between decoding speed and hardware complexity [19]. The biggest challenge is the large message memory consumption it introduced.…”

Section: Introductionmentioning

confidence: 99%

A low complexity LDPC-BCH concatenated decoder for NAND flash memory

Chen

Sha

Zhang

et al. 2018

IEICE Electron. Express

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Low-density parity-check (LDPC) codes are widely used in NAND flash memory as an advanced error correction method due to their excellent correcting capability. The major challenge is the error floor problem. Dispersed array LDPC (DA-LDPC) code is highly structured and provides implementation convenience due to its regularity. In this paper, it is shown that the constructed (18289, 16384) DA-LDPC code suffers the error floor at BER of 10 −9 , which is far from the demand of flash memory error control. Carefully observing the error patterns in the error floor region, we propose a concatenation of BCH code to alleviate this issue. The error floor has been successfully brought down to BER of 10 −14 by concatenating a BCH code with correcting capability of 14 bits. Compared to the standalone LDPC decoder, the concatenated decoder only consumes 7% extra hardware and the code rate penalty is less than 1%. Meanwhile, hardware implementation has shown that the throughput can achieve 3.52 Gbps with 6 iterations under a clock frequency of 200 MHz.

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Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Cited by 32 publications

References 10 publications

A Survey of FPGA-Based LDPC Decoders

A Survey of FPGA-Based LDPC Decoders

Parallel concatenated Gallager codes matrix and the effect of interleaver

A low complexity LDPC-BCH concatenated decoder for NAND flash memory

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