We have designed and implemented the 0 1 0 0 0 1 0 1 0 LDPC decoder with memory-reduction method to 1 0 1 0 1 0 0 0 0 achieve high-throughput and practical hardware size 0 0 0 1 0 1 0 1 0 for long code-length. The decoder decodes (3,6)-h 1 0 0 0 0 1 0 1 11520-bit regular LDPC codes using modified min-0 0 1 0 1 0 0 0 1 sum algorithm. The decoder achieves a throughput of I 0 0 1 0 0 1 0 0 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates. Fig. 1. Parity Check Matrix.
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