A Survey of FPGA-Based LDPC Decoders

Abstract

Abstract-Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their insystem programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, processing latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoders.

Hardware-Aware Sum-Product Decoding in the Decision Domain

“…The update rule (5) in the L-domain needs computations of the tanh and tanh −1 functions. In order to circumvent them, we transform the SP decoding in the L-domain to that in the D-domain, which is the image of the tanh function.…”

“…The update rule (5) in the L-domain may be implemented with LUTs of the tanh function when an FPGA is used. Similarly, LUTs may be used to compute the channel messages {D n } in the D-domain.…”

“…In practical communication systems, SP decoding needs to be implemented in hardware devices such as applicationspecific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) [5]. In implementing the SP decoding in the logarithm (L) domain, we face two difficult issues [6]- [8]: (i) how to implement the tanh and tanh −1 functions and (ii) how to quantize messages in the L-domain.…”

VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate

“…For Virtex FPGA from Xilinx, the complexity is expressed in Slice and LUT, the approximate formula used is LE = Slice* 4*LUT * 0.83 [16].…”

Design Trade‐Offs for FPGA Implementation of LDPC Decoders

“…Therefore, LDPC codes are used in a wide range of standards for both wireless communication [2]-WiFi, WIMAX, DVB-S2, etc-as well as for FLASH-based storage systems [3].…”