Field - Programmable Gate Array 2017
DOI: 10.5772/66085
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Design Trade‐Offs for FPGA Implementation of LDPC Decoders

Abstract: Low density parity check (LDPC) decoders represent important throughput bottlenecks, as well as major cost and power-consuming components in today's digital circuits for wireless communication and storage. They present a wide range of architectural choices, with different throughput, cost, and error correction capability trade-offs. In this book chapter, we will present an overview of the main design options in the architecture and implementation of these circuits on field programmable gate array (FPGA) device… Show more

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“…These tradeoffs induce network designers to compromise between decoder operation line rate and precision, within the available limited silicon hardware resources. Block RAMs (BRAMs) are the fundamental array storage resources in FPGAs, where stateof-the-art BRAMs have a read and a write port with independent clocks, implying that a single BRAM can perform a maximum of two read/write operations in parallel [2,74]. Therefore, to realize a high degree of parallelism required in protocol sized LDPC codes, many BRAMs must be used in parallel to access the BP LLRs.…”
Section: Classical Bp Decoder Limitationsmentioning
confidence: 99%
“…These tradeoffs induce network designers to compromise between decoder operation line rate and precision, within the available limited silicon hardware resources. Block RAMs (BRAMs) are the fundamental array storage resources in FPGAs, where stateof-the-art BRAMs have a read and a write port with independent clocks, implying that a single BRAM can perform a maximum of two read/write operations in parallel [2,74]. Therefore, to realize a high degree of parallelism required in protocol sized LDPC codes, many BRAMs must be used in parallel to access the BP LLRs.…”
Section: Classical Bp Decoder Limitationsmentioning
confidence: 99%