ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems

Iqbal, Syed Muhammad Zeeshan; Liang, Yuchen; Grahn, Håkan

doi:10.1109/l-ca.2010.14

Cited by 85 publications

(26 citation statements)

References 3 publications

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“…We use 39 diverse workloads from several benchmarking suites: MiBench [20], which is a suite of representative embedded workloads; LMbench [21], which contains microbenchmarks for activating and testing specific microarchitectural behaviours, such as memory reads at a specific level of cache; Roy Longbottom [22], which contains many multi-threaded workloads that make heavy use of the NEON SIMD processing unit and OpenMP; ParMiBench [23], which is a multi-threaded version of MiBench; and, ALPBench [24], which contains complex, parallel multimedia workloads.…”

Section: Methodsmentioning

confidence: 99%

Thermally-aware composite run-time CPU power models

Walker

Diestelhorst

Hansson

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations in typical performance monitoring counter (PMC) based power modelling approaches and illustrate how an improved model formulation results in a more stable model that efficiently captures relationships between the input variables and the power consumption. Using this as a solid foundation, we present a methodology for adding thermal-awareness and analytically decomposing the power into its constituting parts. We develop and validate our methodology using data recorded from a quad-core ARM Cortex-A15 mobile CPU and we achieve an average prediction error of 3.7% across 39 diverse workloads, 8 Dynamic Voltage-Frequency Scaling (DVFS) levels and with a CPU temperature ranging from 31• C to 91• C. Moreover, we measure the effect of switching cores offline and decompose the existing power model to estimate the static power of each CPU and L2 cache, the dynamic power due to constant background (BG) switching, and the dynamic power caused by the activity of each CPU individually. Finally, we provide our model equations and software tools for implementing in a run-time manager or for using with an architectural simulator, such as gem5. I. INTRODUCTIONWhile mobile devices are required to be ever-more energy efficient, mobile CPU designs are becoming more complex in order to achieve the ever-increasing performance demand of new applications. Key to saving energy is the system's runtime manager (RTM), which controls CPU energy-saving techniques (such as dynamic voltage frequency scaling [DVFS] or heterogeneous cores [e.g. ARM's big.LITTLE technology]) in order to trade off power and performance based on the current conditions and requirements. However, in order to make these trade-offs effectively, run-time knowledge of how power is being consumed is essential. A fast and accurate power model, that is able to predict the current power consumption at runtime, can therefore be used with a run-time manager to make significant energy savings [1].Previously, top-down regression-based models using performance monitoring counters (PMCs) as inputs have been widely shown to be effective in estimating CPU power [2]- [13]. Topdown approaches use power measurements from real devices and predict this measured power using metrics. Therefore they

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Section: Methodsmentioning

confidence: 99%

Thermally-aware composite run-time CPU power models

Walker

Diestelhorst

Hansson

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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“…As an alternative, all the task's data must be replicated, as the parent task can not neither have its data modified nor be blocked until its child finishes. Table III presents two benchmarks of the ParMiBench Suite [16]. These benchmarks were ported to HellfireOS, and as the overhead is being measured here, tasks were configured as best effort.…”

Section: A Implementation and Validation Methodologymentioning

confidence: 99%

Customizable RTOS to support communication infrastructures and to improve design space exploration in MPSoCs

Aguiar

Johann

Magalhães

et al. 2013

2013 International Symposium on Rapid System Prototyping (RSP)

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Multiprocessed System-on-Chip (MPSoCs) have become a recurrent implementation alternative to modern embedded systems and, lately, have counted on resources previously available only on general purpose machines. In this context, it is possible to highlight that many techniques formerly adopted in general-purpose computers have been studied and adapted to the embedded reality. Thus, embedded communication infrastructures such as buses and networks-on-Chip (NoCs) are based on general-purpose solutions and are widely accepted for embedded systems. Also, embedded systems make use of Operating Systems (OS), as they provide standard interfaces to access hardware resources, including the communication facilities. However, although the underlying communication infrastructure can differ in order to improve a given metric, such as performance, power or area, it is desirable that the software layer remains the same, especially in terms of the application's and OS's code improving the overall software quality. Still, certain OS parameters can directly influence on the overall system performance. This paper presents a highly configurable Real Time OS (RTOS) that implements a communication protocol to provide a transparent communication interface for both bus-and NoC-based MPSoCs' applications.

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“…We simulate six SPLASH-2 [22] benchmarks, six PAR-SEC [3] benchmarks, four Parallel-MI-Bench [7], a TravellingSalesman-Problem (tsp) benchmark, a Depth-First-Search (dfs) benchmark, a Matrix-Multiply (matmul) benchmark, and two graph benchmarks (connected-components & community-detection) [1] using the Graphite multicore simulator. The graph benchmarks model social networking based applications.…”

Section: Application Benchmarksmentioning

confidence: 99%

“…So, we explore a mechanism that tracks the locality information for only a few cores, and classifies a new core as a private or remote sharer based on a majority vote of the modes of the tracked cores. Figure 13 plots the completion time and energy of the benchmarks with the Limited k classifier when k is varied as (1,3,5,7,64). k = 64 corresponds to the Complete classifier.…”

Section: Limited Locality Trackingmentioning

confidence: 99%

The locality-aware adaptive cache coherence protocol

Kurian

Khan

Devadas

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

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Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future processors. We propose a scalable, efficient shared memory cache coherence protocol that enables seamless adaptation between private and logically shared caching of on-chip data at the fine granularity of cache lines. Our data-centric approach relies on inhardware yet low-overhead runtime profiling of the locality of each cache line and only allows private caching for data blocks with high spatio-temporal locality. This allows us to better exploit the private caches and enable low-latency, low-energy memory access, while retaining the convenience of shared memory. On a set of parallel benchmarks, our lowoverhead locality-aware mechanisms reduce the overall energy by 25% and completion time by 15% in an NoC-based multicore with the Reactive-NUCA on-chip cache organization and the ACKwise limited directory-based coherence protocol.

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ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems

Cited by 85 publications

References 3 publications

Thermally-aware composite run-time CPU power models

Thermally-aware composite run-time CPU power models

Customizable RTOS to support communication infrastructures and to improve design space exploration in MPSoCs

The locality-aware adaptive cache coherence protocol

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